from "Intel® 64 and IA-32 Architectures Software Developer’s Manual", we know that in the latest CPU, TSC(timestamp counter) is constant and invariant. It means that TSC in each core will tick at a constant rate. If each core receives the RESET signal at the same time, then TSC is synchronized.
However, it is not clear from the manual whether each core is able to receive the RESET signal at the same time, especially in a multi-socket (like 4, or even
From the description of "Section 17.17.3 Time-Stamp Counter Adjustment" in the manual, it seems to guarantee that TSC is synchronized across sockets as long as TSC_ADJUST is the same across each core.
So, is TSC guaranteed to be synchronized? How do TSC synchronize across sockets? Can TSC reflect real time (like, building transactions on TSC) ?
Thank you for posting on the Intel
I would like to let you know that we have a specific forum for this kind of issue and product, it is called the Intel Developer Zone. There you will receive the appropriate support on this and other concerns you may have related to this product.
Here you will find the links to access the website and the community forums:
Also, if you need this information for developing a project, you can open an Intel premier support case with us, this support is provided only if you have an IPS account.
In case you don’t have an account, you can contact a distributor and ask for a FAE.
Hope this information is useful, please keep in mind that this thread will no longer be monitored by Intel.
Intel Customer Support Technician