ALTLVDS_RX->LVDS serdes Link Training

[Altera_Forum]

Implementing Receiver interface. From transmitter we have 8 LVDS data channel and 1 LVDS sync channel. From sync channel we use to get training pattern which will be available in data channel for link training. 

 I have used "ALTLVDS_RX" component for each LVDS data channel and sync channel (9's ALTLVDS_RX). I have query that how to do the link training?   In ALTLVDS_RX i have observed that we have "rx_data_align" which will be input port after making tick while generating component. So, from where this input is controlled or generate. What mechanism or logic is required for this, if it will resolve our bit align/ bit slip for link training. Else what we need to do for this....:confused::confused::confused:

[Altera_Forum]

All three ADC chips must be driven by the same source clock, so the DCO of the one you use has a 0PPM difference from the other chips. From your description, there is no difference between the three ADCs, so there's no reason I could say one is better, but no, I assume they're laid out similar and it wouldn't matter. 

I assume DCO is the clock, what's the FCO? I'm not sure without knowing it's functionality.

[Altera_Forum]

--- Quote Start ---  All three ADC chips must be driven by the same source clock, so the DCO of the one you use has a 0PPM difference from the other chips. From your description, there is no difference between the three ADCs, so there's no reason I could say one is better, but no, I assume they're laid out similar and it wouldn't matter. I assume DCO is the clock, what's the FCO? I'm not sure without knowing it's functionality.  --- Quote End ---    Hi Rysc,  Yes, DCO is the source sycnrous clock, together with the output LVDS data. The FCO is the fram clock output, which will indicate the data word edge. Normally, FCO would be process like LVDS output data channel. That's why i said it will consume fpga lvds_rx channels.

[Altera_Forum]

--- Quote Start ---  Hi Rysc, Yes, DCO is the source sycnrous clock, together with the output LVDS data. The FCO is the fram clock output, which will indicate the data word edge. Normally, FCO would be process like LVDS output data channel. That's why i said it will consume fpga lvds_rx channels.  --- Quote End ---    If the ADC used has a loadable testpattern you could do without the FCO signals and do a bitslip alignment on each ADC channel.

[Altera_Forum]

In fact, that is what you want to do. Since each channel calibrates independently, it's possible for them to be off from each other. I'll admit, this is a strange thing, as I recommend doing this alignment, but I know of users who have put down DPA designs, never calibrate, and have it work. I think they are at speeds and have layouts where the DPA always aligns to the center of the same bit. Note that the DPA chooses a sampling clock for the most margin. Let's say in one channel it thinks everything is fine, but the channel next to it there are some slightly different delays, and it decided to choose a sampling clock one cycle over, in which case the bits are not aligned between channels. Sending a known patter(which most ADCs do, as far as I know) can allow you to calibrate, and would also alleviate the need for FCO.

[Altera_Forum]

Hi josy&Rysc, 

 Thanks a lot. I'll try each possibility after i receive the board.  Best Regard