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ALTLVDS buffer implementation

Altera_Forum
Honored Contributor II
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I'm using an altlvds_rx receiver in Cyclone III with external PLL. For the buffer implementation I can choose between RAM, MUX and LE. Could there be a reason to make a choice other than resource usage? 

 

There's no documentation on this issue available.  

Well, at least I can't find it.  

 

Cheers, Ton
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Altera_Forum
Honored Contributor II
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Well there's one good reason not to use RAM buffer. It adds a variable data latency to rx_out after a reset or power cycle. 

 

The MUX and LE and they both give a FIXED latency of 3 slow clock periods. 

 

The LE buffer implementation uses a lot of resources, so I stick with the MUX buffer implementation. 

 

See also another thread I've posted today. 

 

Cheers, Ton
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Altera_Forum
Honored Contributor II
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Many ALT_LVDS users probably wonder what's the purpose of a buffer with Cylone III LVDS, because they never got in touch with it. Actually, it's only present with odd deserialization factors. 

 

I once had the bad idea to build a desrialization factor 14 LVDS receiver (which is not supported by the MegaFunction directly) from a "factor 7" block. But the behaviour of the odd deserialization factor receiver was so strange, that I preferred an own deserializer design.
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Altera_Forum
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Thanks FvM. So it is the odd deserialization factor. You're right. I use a deserialization factor of 9. What a mistake. Next time I will certainly use even factors, that's for sure.  

 

Do you know if there's any detailed additional information on this topic? 

 

Cheers, Ton
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Do you know if there's any detailed additional information on this topic? 

--- Quote End ---  

 

I fear, there isn't. I was surprized myself, when I was aware of the special properties of the odd factor LVDS receiver and looked inside the generated RTL. I decided, that it wasn't an appropriate solution for my problem. Generally, because Cyclone soft LVDS is based on double data rate (DDIO) registers, the fast clock can be aligned with the slow clock only for every second data word. So some kind of special processing is required. 

 

Regards, Frank
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