Cascading CPLDs on different PCBs

[Altera_Forum]

I'm designing a basic harness continuity checker based on shift registers implemented in Max V CPLDs. I'm aiming for a modular/extendable PCB design for the project as it has several benefits (cost, less complexity). 

 A uC communicates with my CPLDs using SPI. What I'm not sure about is how to best cascade these CPLDs in order to obtain a larger shift register. In a 144-pin TQFP, I only have 114 IO pins. Therefore, I can only implement a 114-bit Serial In Parallel Out or a Parallel In shift register. But by cascading these 114 IO devices I can obtain much larger shift registers.  However, I'd like to place these additional CPLDs on a different PCB. This has the advantage that I can simply extend the device when I need. On smaller harnesses, a single 114 test-point PCB will suffice. On larger ones, I can cascade. At the moment, the CPLD is really just a shift-register. But in the future I'm hoping to implement a state-machine that can possibly implement more functions, like checksum to verify the contents sent by the uC etc. But that's for later and all I know is that I'd just use SPI for communication.  As the CPLDs need SPI for communication, I am guessing that I need to pass these onto the cascading shift register i.e. each device will have a Serial Out (SO) pin. But it will also need to pass CLK, Chip Select and even a SI/MISO pin incase the uC needs to read back the shift register contents.   I think buffering the signals would be good practice. But what would be the best way to actually connect the PCBs together? I suppose these really depends on the speed of operation. Fortunately, speed isn't an issue and therefore I'm operating at a very low frequency - just 62.5kHz. I'd like to be able to increase this, perhaps to 500kHz. I don't think I'll need any beyond that. At such frequencies, what's the best way to cascade PCBs and CPLDs?  Please note, I'm aware that I can purchase a large 324-pin device. I'm afraid, I can't really use that as there is no way to inspect BGAs here locally. So I'm sticking with TQFP packages.  I'm also aware that the topic, perhaps, mostly pertains to pcb-layout but I'm hoping I can get some CPLD/FPGA centric advice here regarding what signals I need to send as I'm not so sure about that.  Would appreciate any responses.

[Altera_Forum]

--- Quote Start ---   You don't. Each CPLD synchronizes the serial data to its own clock domain. The I/Os would update on the rising-edge of the shift clock, as detected in the synchronized domain (within a couple of clocks of each oscillator), or you can use the serial clock to update it.  --- Quote End ---    Ah, so each daughter-board as it's own oscillator. I think I'll go with an oscillator then.  But if feeding the clock to just one pin is ok, why does the CPLD have as much as 4 dedicated pins for the clock? Not that I'm complaining, just want to know.

[Altera_Forum]

--- Quote Start ---   But if feeding the clock to just one pin is ok, why does the CPLD have as much as 4 dedicated pins for the clock? Not that I'm complaining, just want to know.  --- Quote End ---    Many systems have more than one clock :)  Cheers, Dave

[Altera_Forum]

This TI article is somewhat relevant to this discussion: 

 "Extending the SPI bus for long-distance communication"  http://www.ti.com/lit/an/slyt441/slyt441.pdf