Component TCL file in Qsys

[Altera_Forum]

Hi, 

 I have designed the component's TCL file. It has one avalon slave port and avalon master port. I want to read the Base Address of my Avalon Slave Port in TCL file.  When Qsys is generated, master port of another component will get connected to my Avalon Slave Port. How can I get the Base Address of this Slave Port?  Thanks in advance..  Regards, Harsh.

[Altera_Forum]

This information is in the .sopcinfo (XML) file that Qsys produces when it performs a "Generate..." 

 If you're doing it in TCL, just use one of the XML packages to read in the .sopcinfo file and extract the pertinent information.

[Altera_Forum]

Hi ted, 

 Thanks for your reply!!  Yes, you are right that I can find the related information from the .sopc file. More precisely I can say, .sopc file is generated in generation phase (last phase) of Qsys and I want to read that Base Address in the TCL file (_hw.tcl) of my component ( earlier phase i.e. validation_callback or elaboration_callback ).  Is there any way?

[Altera_Forum]

Note that you don't actually need the address of your component's Avalon or AXI slave port. QSYS will assign the address when your component is put to use in a system. The HDL code for your component needs to be written as if starting at zero. The Avalon fabric will handle the address mapping.  

 In the event you are using the address of your component from the master port of another component, it is better to have that base address be programmable so that your components can be placed into systems without worrying about matching specific addresses.

[Altera_Forum]

--- Quote Start ---  Note that you don't actually need the address of your component's Avalon or AXI slave port. QSYS will assign the address when your component is put to use in a system. The HDL code for your component needs to be written as if starting at zero. The Avalon fabric will handle the address mapping.   In the event you are using the address of your component from the master port of another component, it is better to have that base address be programmable so that your components can be placed into systems without worrying about matching specific addresses.  --- Quote End ---    Thanks for the reply..  Yes, you are right that I should not worry about the addressing because it is handled by Avalon fabric. But I am using the base address of my Avalon Slave Port in a calculation to configure the DMA ( via another Avalon Master Port ).   I have an alternative by adding a register for base address in my HDL module which will be written by Nios Processor. But if I am able to get that address in the Validation or Elaboration phase of Qsys then its a great !!  Regards, Harsh.