Cyclone 4 deserialization, banks, pll

[Altera_Forum]

Dear Gurus; 

  I have 1 Cyclone IV GX EP4CGX150(DF27C7)  This Cyclone IV is connected to 6 x Cyclone III (C40F484)  All of these 6 Cyclone IIIs will send 4 bit LVDS serialized input data and a clock(120mhz)  I need to deserialize 4 bits of data with their respective clocks by Cyclone IV GXEP4CGX150   questions  1- Which banks should I use for these 30pins (4 bit data and clock inputs) x6  2- What is the number of PLLs that I need to use while desialization     PS: I used to do this with Xilinx Spartan 6 but I am new to Altera.

[Altera_Forum]

I guess, the accompanying clock is a frame (slow) clock. Then each receiver needs a separate PLL to generate a bit clock for the respective channel In other words, you can't implement 6 receivers in a single Cyclone IV. 

 If some prerequisites are met (>600 MBPS bit rate, coding with maximum run length, embedded sync patterns), GX receivers may be also utilized.

[Altera_Forum]

But in the `clock networks and plls in the cyclone devices` datasheet it is stated that 

`Cyclone 4 GX device contain up to 8 general purpose PLLs and multipurpose PLLs.`  Cant I generate 6 receivers using these 8 PLLs

[Altera_Forum]

--- Quote Start ---  Cyclone 4 GX device contain up to 8 general purpose PLLs and multipurpose PLLs  --- Quote End ---   Right, I didn't notice this. I must confess, I'm not familiar with these C IV extensions. Sorry for the confusion.

[Altera_Forum]

Yes there will be slow clock and there will be a fast clock 

With the fast clock => deserialization will be done With the slow clock => paralel data(N:0) will be latched for each slow cycle clock

[Altera_Forum]

The standard method is to transmit the slow clock from the source and generate the fast clock at the receiver side. However, if you transmit both, you don't necessarily need a PLL. But the fast clock should be alligned suitable for deserilization.

[Altera_Forum]

What about the bank selection 

Should I select different banks for the inputs? Can two plls drive the same bank with different fast clocks. Or it does not matter at all?   regards

[Altera_Forum]

I assume yes, but the details are described clock network chapter of the hardware manual. I suggest to set up a test design in Quartus and check if the bank assignments are accepted.

[Altera_Forum]

Yes that`s what I am going to do.  

I was just trying to find a quick response since I am new to the topic