Cyclone II PLL ESD Sensitivity

[Altera_Forum]

Hi all! 

 I have a problem with a Cyclone II design.   I have taken a lot of measures against ESD and power supplies remains stable when discharging to the board connectors.   I am however experiencing that the Cyclone's PLL's goes out of lock, even at very low ESD levels. The clock is supplied by a nearby oscillator.   The PLL supplies are fed thrugh a ferrite bead and decoupled by 1uF X7R and 1nF C0G.   Does anyone have an idea why this is so and/or a suggestion how to improve the immunity?   Thanks a lot   Peter

[Altera_Forum]

With Cyclone II, PLL supply interferences, including ground bounce affecting the PLL supply are the most likely cause for PLL loose of lock, according to my experiences. Interferences at the input clock are another possible reason.  

 Generally, the ESD may cause supply spikes, that are slow enough to cross the PLL supply filter. But without knowing your supply bypass topology and board layout, it's hard to decide. I expect, that you have a multilayer PCB with a continuous ground plane and effective bypass capacitors at all supply pins connected directly to this plane?   To suppress possible interferences at the input clock, you may solder a small crystal oscillator for test as near as possible to the FPGA, only connecting directly to FPGA pins.  As another point, ESD are allowed to cause temporary disturbances, that can be handled without user interaction in usual EMC rules. It's mainly a matter of software design to meet this requirement, at least as a last ressort to avoid a complete redesign.

[Altera_Forum]

I already tried with a TCXO oscillator just next to the clock input. But it did not help. 

 I think you are right about the ground bounce, unfortunately it is quite difficult to impove in the current design.   I'm aware that temporary disturbances are allowed and a software workaround may be the solution.   I have based the FPGA internal reset signal on an external reset signal and the PLL "Locked" signal. If the PLL goes out of lock, then I reset all state machines. This will make the disturbance not just temporary as I will loose communication.   I believe it is best practice to reset the system if the PLL goes out of lock, but it actually seems that the state machines survives a discharge if I don't. Is it safe to run if the PLL goes out of lock?

[Altera_Forum]

You should use safe coding for the state machines, otherwise a clock timing violation may cause a state machine to get trapped forever in an illegal state. If your design doesn't depend on the phase relation of different PLL output clocks, a PLL reset isn't absolutely required, I think.

[Altera_Forum]

Will it be enough to enable the "Safe State Machine" parameter in the analysis and synthesis settings in Quartus? Will it implement all states then?

[Altera_Forum]

Yes, according to the documentation. The basic point is to synthesize transitions for all possible state variable encodings, not only the legal states. This implies only a minor extensions to the FSM logic, but isn't done in standard encoding.

[Altera_Forum]

Thanks a lot for your answers, they have been helpful. 

 Regards,   Peter