Cyclone IV JTAG Working, Configuration Not

[Altera_Forum]

This is the first time I have had a design around an Altera part not load properly. I am sure it is my fault, but I am running out of things to check. This is with a Cyclone IV EP4CE10E22C8N. Both of my design prototypes are showing the same strange behavior.  

 When I connect the USB Blaster and run JTAG chain tests in Quartus, the tests pass without any errors. When I configure over JTAG in the Quartus Programmer, it tells me the configuration was successful. However, the hardware does not show it.   The code is just written to tie a few output pins high or low. No PLLs or clocks are involved yet. This is typically the first code I try to load onto a board just to make sure the configuration process works and the project is setup correctly. In this case the output pins do not follow the code. Whether I have pins tied high or low in code, the outputs are intermittently showing up as either 0.45V or 0V on a voltmeter after configuration. VCCIO for all the banks is 2.5V, and the rail itself looks good despite the bad output readings. The I/O standard for the project is set to 2.5V.   The 1.2V core voltage looks good.   I happen to have a serial flash connected, though it does not have a configuration stored on it yet. If I try to program the serial flash through the FPGA, two things happen. First, Quartus shows that configuration of the Flash IP Loader is successful over JTAG. Then, it gives me the error "Flash Loader IP not loaded on device 1"  I have nCE tied low, while nCONFIG, CONF_DONE, and nSTATUS each have a 10k pull-up resistor to 2.5V. Looking at the signals with pull-ups after a configuration over JTAG, I see this: nCONFIG: 2.5V (expected) nSTATUS: 2.5V (expected) CONF_DONE: sometimes 2.5V, sometimes 0V, but stable until the next configuration attempt.   I have unused inputs set to "input tri-stated with weak pull-up"  Does this behavior ring any bells with anyone?

[Altera_Forum]

I guess no one has solved this yet... 

 I am currently running into the same issue. I get the "success" messages when programming the config PROM with a JIC file. I can also run a verify immediately after, and even see my device signal "CONFIG DONE".  However, if I power cycle my device, I never see "CONFIG DONE", but I see a ton of traffic on the Serial interface between the CONFIG PROM and the FPGA. If I run a verify at this point, I get the Flash Error.  Thoughts?

[Altera_Forum]

Hello, 

Is this issue solved? I am also facing a similar issue.

[Altera_Forum]

I eventually ran out of things to try. I went for outside help through an Altera applications engineer, but they also ended up stumped. I scrapped the boards. I've done two more Cyclone IV designs from scratch since then, and both of those worked fine on the first try. The most significant electrical difference on the boards that didn't work was that they used only two power rails (1.2V core and 2.5V VCCA+I/O) instead of three (1.2V core, 2.5V VCCA, and 3.3V I/O). That could be a hint, but I wasn't able to find any reason that a two-rail design would be more problematic than a three-rail design. I figured the problem was just a fluke of some kind (bad PCBs, spoiled parts, or a problem during assembly) and moved on. It stings to be out $400 on non-working prototypes, but it could be worse. At least they weren't Stratix parts.

[Altera_Forum]

Hi, 

according to the serial configuration device datasheet (I assume these are used) the EPCS devices are recommended for operation voltages between 2.7 to 3.6VDC, thus supporting the 3.3V and 3.0V I/O standard. Thus the problem might be just wrong power at the Configuration EEPROM....

[Altera_Forum]

Hello Carlhermann 

I think we can ignore the voltage to configuration device as the JTAG configuration itself is not happening properly. To isolate this issue, I have even removed the EPCS Flash and tried the JTAG configuration still the result is same.  As skrasms pointed out, the difference I find here is that the configuration (JTAG and AS) banks are powered from 2.5V instead of 3.3V. Does this kind of a situation require any special consideration?

[Altera_Forum]

During my troubleshooting, I took the serial configuration flash completely off a board and still couldn't get the FPGA to run from a JTAG configuration. As a side note, the M25P40 part from Micron/Numonyx is a drop-in replacement for an EPCS4 and supports 2.3V to 3.6V. That was my plan for serial configuration on the 2.5V board.

[Altera_Forum]

--- Quote Start ---   As a side note, the M25P40 part from Micron/Numonyx is a drop-in replacement for an EPCS4 and supports 2.3V to 3.6V.  --- Quote End ---     No they don't go down to 2.3V (at least any of the device data sheets I've looked at).  I was recently stumped with some recent experiments to prove an M25P16 was an acceptable replacement for a Spansion part that was going obsolete. After much hair pulling I realised I'd set the supply to the config prom wrongly, it was at ~2.2V. The Spansion part worked but the M25P16 didn't. The M25P data sheet said >2.7V, when I fixed the supply to 2.8V it worked finw.  I'd be keen to find an EPCS16 substitute that works down to 2.5V, what parts were you looking at?   Nial.

[Altera_Forum]

--- Quote Start ---  No they don't go down to 2.3V (at least any of the device data sheets I've looked at).   --- Quote End ---    Fortunately you are mistaken. This can be verified by a quick search on Micron's website or Digi-Key. I have attached a data sheet from Micron. The M25P40 is 2.3V to 3.6V. Note that this is the M25P40 (replacement for an EPCS4), not the M25P16. The M25P40 is large enough to store the configuration for an EP4CE10, which is what I was using.

[Altera_Forum]

Hi, 

don't wont to bother anyone, but comparing the M25P40 data (2.3V, Grade6 => fmax = 25MHz acc. page 42) with the cyclone's internal oscillator's frequency (40MHz, ch.8) there might be a mismatch which most likely will not cause any Problems in real life many times, but it is not 100% save, is it?

[Altera_Forum]

--- Quote Start ---  Hi, don't wont to bother anyone, but comparing the M25P40 data (2.3V, Grade6 => fmax = 25MHz acc. page 42) with the cyclone's internal oscillator's frequency (40MHz, ch.8) there might be a mismatch which most likely will not cause any Problems in real life many times, but it is not 100% save, is it?  --- Quote End ---    That’s a great spec to check. I find that it meets or exceeds Altera’s EPCS parts running at 3.3V according to printed specifications.   The maximum “read clock” frequency for Altera EPCS parts at 3.3V is 20 MHz, and the maximum “fast read clock” frequency is 40 MHz. In comparison, the M25P40 2.3V operation section of the spec shows a maximum “read clock” frequency of 25 MHz and maximum “fast read clock” frequency of 40 MHz.   That makes the M25P40 at 2.5V appear at least as guaranteed as an EPCS4 at 3.3V.

[Altera_Forum]

Hi, 

acc. to the Cyclone IV Handbook, the Cylone IV E generates the DCLK from internal oscillator with 40MHz. The slow option with 20MHz is for GX devices only. Additionally the "E" types suport 2.5V/3.0V/3.3V configuration voltage standard.  The EPCS configuration device is specified for up to 40MHz for 2.7V to 3.6V with no dependency between fmax and Vcc, thus it is not for use with 2.5V configuration voltage designs... Comparing the specifications one might wonder which constellation / device is the "to be used one" for the 2.5V AS configuration with Cyclone IV..

[Altera_Forum]

--- Quote Start ---  Fortunately you are mistaken. This can be verified by a quick search on Micron's website or Digi-Key. I have attached a data sheet from Micron.  --- Quote End ---    Unfortunately I wasn't mistaken, I've attached the latest data sheet for the M25P16 I've just downloaded from the Micorn web site, 2.7V to 3.6V single supply voltage.   It looks like there may be some devices that'll work down to 2.5V but you're going to have to be careful.   I think I have to use fast AS to meet the PCIe reset restriction too which is another aspect I have to consider.   Nial.

[Altera_Forum]

I don't exactly understand your reasoning. 25P40xx6 is specified with 40/25 MHz (FAST READ/STANDARD READ) down to 2.3V, EPCS4 with 40/20 MHz downto 2.7V.

[Altera_Forum]

Hi, 

well the question is (and I did not really paid attention to Note 2 on page 42) what is the difference between clock frequency for commands fc and clock frequency for Read commands fr if commands include Read Bytes...  Doesn't fc already includes the separately referenced read command, thus there is no need to specify any fr?  Just wondering (and blaming myself for less attention...)

[Altera_Forum]

My point is that EPCS4 is even slower than 25P40 by specification, thus I assume the FPGA loader uses FAST READ, but I didn't check. 

 P.S.: I didn't notice that the same point is already mentioned in post# 11.

[Altera_Forum]

I have the same problem. I used Altera EP4CE6F17I7N, FBGA256 and EPCS4. I have all three supply voltage (VCCIO= 3.3V, VCCA= 2.5V, VCCD_PPL1, VCCD_PPL2, and VCCINT =1.2V). MSEL = 010. I was successfully loaddown firmware to EPCS4 use as Active Serial. However, when I recylce the power the CONFIG_DONE it struck low. I try JTAG didn't work. Please give advice.

[Altera_Forum]

--- Quote Start ---  I have the same problem. I used Altera EP4CE6F17I7N, FBGA256 and EPCS4. I have all three supply voltage (VCCIO= 3.3V, VCCA= 2.5V, VCCD_PPL1, VCCD_PPL2, and VCCINT =1.2V). MSEL = 010. I was successfully loaddown firmware to EPCS4 use as Active Serial. However, when I recylce the power the CONFIG_DONE it struck low. I try JTAG didn't work. Please give advice.  --- Quote End ---   Hello, ptran2012 ! What was the cause of the problem?