Cyclone IV reconfiguration

[Altera_Forum]

Hi, 

 do Cyclone IV FPGAs support software programmable reconfiguration, or any other form of the run-time reconfiguration?

[Altera_Forum]

--- Quote Start ---   do Cyclone IV FPGAs support software programmable reconfiguration, or any other form of the run-time reconfiguration?  --- Quote End ---    Yes, all FPGAs support reconfiguration. Whether or not your particular board design can handle it is another question.  FPGAs can be configured using their JTAG connection, or from an external serial EEPROM, or from an external Flash device.  Did you have a particular development board in mind that you had a specific question about?  Cheers, Dave

[Altera_Forum]

No, i meant run-time reconfiguration. Specifically, i want to implement a learning model on an FPGA in such a way that when the model will change its parameters, the FPGA will reconfigure itself accordingly. According to the Altera pdf (i cannot post links, so just google "software programmable reconfiguration" and click the first link) this reconfiguration should be controlled by the NIOS II embedded processor.

[Altera_Forum]

--- Quote Start ---  run-time reconfiguration   --- Quote End ---    Did you read the document?  This is not FPGA reconfiguration, its the fpga configuration. The hardware is simply designed to be flexible. That means that more FPGA logic is likely required to implement the functionality.  Calling this 'software reconfiguration' is just marketing hype.  What function did you need to reconfigure?  Cheers, Dave

[Altera_Forum]

I am new to the FPGA stuff, so i don't know it is possible to use FPGA for the task i am struggling with. The subject of the task is to model the neuroevolution remotly controlled by a desktop PC. The population consists of a set of wheeled robots. During the entire process of neuroevolution, the NIOS II soft processor has to be implemented on an FPGA.  

 My idea of the whole process consits of the following steps:  1. The new structure of the neural network is downloaded by the NIOS processor from the PC and implemented on the rest of the FPGA.  2. Weights of the neural network are modified by means of a Hebbian leraning rule during the whole life of the individual.  3. Then the fitness of the individual is calculated by the NIOS processor and sent back to the PC.

[Altera_Forum]

I understand that you are referring to partial reconfiguration, as described in this Altera white paper, reconfigurating a part of the logic without interrupting the operation of the remaining part. 

 http://www.altera.com/literature/wp/wp-01137-stxv-dynamic-partial-reconfig.pdf

[Altera_Forum]

That's what i was looking for, but is it possible to do partial reconfigurationon a Cyclone IV FPGA?

[Altera_Forum]

--- Quote Start ---   My idea of the whole process consits of the following steps:  1. The new structure of the neural network is downloaded by the NIOS processor from the PC and implemented on the rest of the FPGA.  2. Weights of the neural network are modified by means of a Hebbian leraning rule during the whole life of the individual.  3. Then the fitness of the individual is calculated by the NIOS processor and sent back to the PC.  --- Quote End ---    Whether or not this maps nicely onto an FPGA depends on what the algorithm looks like. Would this algorithm be classified as requiring lots of parallel logic, for example, have people implemented the algorithm on GPUs?  Do you have the algorithm working on desktop machines? What is the limitation there? Does slicing the processing up into lots of small parallel pieces help? Is there a lot of decision logic required?  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  That's what i was looking for, but is it possible to do partial reconfigurationon a Cyclone IV FPGA?  --- Quote End ---    No.  Its only advertised to be supported on the Stratix V, but there is no software support yet.  Cheers, Dave