NOTE: I have a bunch of screenshots , but when I paste them into a post here it is marked as spam which makes it a real pain to describe my issue.
I am having issues meeting timing when bringing an HPS EMAC into the fabric using a Cyclone V device. In my Qsys project I am using the hps_interface_splitter and gmii_to_rgmii_adaptor cores with the HPS EMAC connected to the splitter core.
I have added an 8nS clock constraint to both RGMII_RX_CLK and RGMII_TX_CLK, but when I build the design I am getting large timing violations on the GMII_RX_DATA[7..0] paths between the output of the fabric register located in the gmii_to_rgmii_adaptor core that connects to the HPS EMAC GMII_RX_DATA pins.
The timing report appears to be telling me that the delay to get the from the fabric to the HPS EMAC GMII_RX_DATA pin is over 7.5nS which is the cause of the timing violation.
Can someone give me any pointers on how I can get this to meet timing please? I am assuming I am doing something inherently wrong here such as having the EMAC incorrectly wired up to the 2 fabric cores.
Also, why can't I paste my screen shots into a forum post? (showing my Qsys project/timing report/chip planner etc)
