Cyclone V LVDS fractional PLL

[Altera_Forum]

Hi all! 

 I explore cyclone V handbook http://www.altera.com/literature/hb/cyclone-v/cyclone5_handbook.pdf. On page 102 (5-12) I see:  Guideline: Use PLLs in Integer PLL Mode for LVDS to drive the LVDS channels, you must use the PLLs in integer PLL mode. The corner PLLs can drive the LVDS receiver and transmitter channels.  Slightly above on that page I read: The corner fractional PLLs can drive the LVDS receiver and driver channels.  I have 2 questions.  Firstly, than i compile project and choose fractional mode for PLL which feeds LVDS output pin, compiler doesn't give an error or even warning.  Is that means that I can ignore guideline or if I choose fractional mode I'll have problems because of additional jitter or smth like that?   Second question is, is there a non-corner PLLs which cannot drive LVDS? I found only corner PLLs in Cyclone V E A4 chip planner.

[Altera_Forum]

The second issue has been resolved, I found non-corner PLLs, for example in Cyclone V E A7.

[Altera_Forum]

So can we use fractional PLL for LVDS transmitter or not on the Cyclone V? If yes, how do you use it because I keep getting fitter error when PLL is set as fractional mode?

[Altera_Forum]

I only used integer PLLs in my Cyclone V projects so far. If one PLL wasn't enough, I used second PLL in cascade. I choose that way because there was an issue with fractional PLL in Cyclone V : http://www.altera.com/literature/es/es_cyclone_v.pdf

[Altera_Forum]

What I have found is that you need to use Quartus 14 new megawizard function "altera pll" and this can be configured as either fractional or integer. But I emphasize that you should use this latest megafunction. -James

[Altera_Forum]

Addittionally, I would add that there was no real migration guide from Altera regarding transitioning from Cyclone IV to Cyclone V . . . in conjunction with the Quartus new releases, the real issue is that you need to use the NEW altera pll megafunction. 

 It would have been helpful to have this information in a migration document, considering that clocking is fundamental to any design.

[Altera_Forum]

I believe the CV IO handbook mentioned something using the integer mode for LVDS...

[Altera_Forum]

Hi, 

 To verify if your specific implementation ie using integer or fractional mode for LVDS can work or not in the Cyclone V device, it is generally recommended to run through Quartus II compilation. Quartus II will help to check against the placement rule and restriction.