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Hi,
I have to interface x16DDR2(MT47H64M16 – 8 Meg x 16) in arria II gx fpga EP2AGX65DF25C6. I am able to interafce single DDR2 using bank 4A(38 user IO pins) & 3A(38 user IO pins). the DDR2 interface has 43 interface signals. But when i try to connect DDR2 signals to bank 5A(50 user IO pins), it gives me an compilation error "can not assign more than 12 output or bidirectional signal in this region". My query is can we interface DDR2 in bank 5A of EP2AGX65DF25C6? thanks, bhupeshLink Copied
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