I am testing the DDR2 controller for the Cyclone II, Quartus 13.0.1, and created a new project. The only code is what was generated by the IP MegaWizard. The only change was in the parameter settings where the data bus is 64-bits instead of 32-bits. Nothing else was changed. the generic DDR2 model in the testbench is correct as far as stdv sizes, etc.
Simulations show the DDR2 mode registers being setup. Then writing. The DQ's and DQS's are always 'Z'.
It appears that the clock generator is not generating the clocks. After tracing through ddr2_ctrl_auk_xxx entities
the "ddr2_ctrl_auk_ddr_clk_gen" should be generating two clocks, 180 degrees out of phase. All that code is two altddio_out instantiations. But, no output clocks!
Any idea?
Swimteam
