DDR2 interface pin planning issue

[Altera_Forum]

Hello, 

 I'm working on a design that is going to use a Cyclone IV FPGA (EPCE75) including migration support for the EPCE30 and EPCE40 devices (F780 package). A lot of IO's will have to operate at 3.3V so it is preferred that interfaces operating at different voltages occupy only one single bank when possible. In my attempt to place the DDR2 interface into bank 7, the following issue occurred:  Bank 7 provides me with 48 usable IO pins which is sufficient for the DDR2 interface as it utilizes 47 pins. After placement and compilation I get the following errors: error (169224): too many output and bidirectional pins per vccio and ground pair in i/o bank 7 when the vref pin g15 (vrefgroup_b7_n2) is used on device ep4ce75f29c8 -- no more than 9 output/bidirectional pins within 12 consecutive pads are allowed when the voltage reference pins are driving in, but there are potentially 10 pins driving out  The Quartus Handbook however addresses this issue and advices to assign an output enable group to the DQ, DQS and DM signals as they all operate only as output or as input at the same time. After I did this however, i got the same error due to the two clock signals which are also defined as bidirectional in order to provide a mimic path for the controller. So in order to determine whether it is still possible to place all signals, i want to know what locations share the same 'VCCIO and ground pairs'. Is this information available somewhere?  After some random pin swapping and compilation I did manage to place a pin configuration which is successfully compiled by Quartus. But how reliable is this? Some additional information concerning VCCIO and ground pairs might help me with this.  Thank you in advance.

[Altera_Forum]

Hi PaulusNL,  

 in my new design I have the same error message and I don't know how to work around.   I already changed the Dqs pin, but I still get the same error. What kind of pin swapping did you do?  I appreciate any help!