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Hello,
I've been stuck on a issue for some time and could use help getting this resolved. I have been developing a RS-232 high-level driver on the DE2-115 using NIOS/QSYS. This driver works as expected when booting from JTAG, but fails to work when booting from Flash. The communications interface (open, write) does not report any errors, but the UART FPGA pins are inactive (idle). I can easily verify this using a scope and the on-board LEDs, which are tied to the UART pins (the LEDs are before RS-232 transceiver). I should also mention that the project includes many other working interfaces such as the Ethernet and LCD. All this works when booting from JTAG and Flash. To simplifying the debugging effort, I reduced the NIOS code to a simple init task as shown below:
void InitialTask( void* pdata )
{
OSPrintfSem = OSSemCreate( 1 );
alt_iniche_init();
netmain();
while( !iniche_net_ready ){
OSTimeDlyHMSM(0, 0, 0, 10);
}
uint32_t data = 0xF0F0F0F0F;
int fd = open(UART_NAME, O_RDWR );
while( 1 ){
write(fd, (uint8_t*)data, sizeof(data) );
OSTimeDlyHMSM(0, 0, 1, 0);
}
}
The QSYS and FPGA project files resemble a reduced version of the DE2_115_WEB_SERVER_MII_ENET0 example. A couple other points: 1. I tried with optimization on (-o3) and off 2. The baud rate is not fixed, but the Qsys default is set correctly 3. I enabled the preprocessor definition: ALTERA_AVALON_UART_USE_IOCTL 4. All code and data sections are mapped to sdram 5. The Qsys design is flat Any ideas?
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You might have IP in your project that isn't licensed. These components will only work when the FPGA is loaded via JTAG and the programmer is running when in use. Check the output messages for stuff about evaluation versions of the parts. I think the more advanced NIOS processors are like this. They simply don't operate unless loaded from JTAG. There is some Altera documentation on how all this works, but I don't recall where it is.
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