DFFEAS (SLOAD vs D input difference?)

[Altera_Forum]

I have been coding a simple FSM and datapath in Quartus II 11.1,  

 When I examine the post-fit netlist in the Technology Viewer, I notice that certain registers/flip flops have the "normal" setup of D data in, CLK, CLRN, but then there are other flip flops where there are additional ports including SLOAD, SCLR, SDATA.  In reading the online resources (DFFEAS Primitive from Altera's website), I can figure out that the functionality of the FF should be the same as if it was wired up in the "normal" setup.  My question is why Quartus is doing this? In certain cases, it seems that using the D input and SDATA inputs allows one to push some logic into the register/flip flop, so I can see the gate saving advantages in those cases.   In other cases, the flip flop/register only has the SDATA wired (nothing into D data in). I don't understand the difference in this case to just wiring it in the "normal" way, and I would like to understand if there are any differences.  Since I am on the novice level, I'm also worried that I might be doing something awkward in the Verilog code that results in the non-"normal" wiring to the SDATA input.   Here's a section of verilog :  always @(posedge clock or posedge reset)  begin  if (reset)  begin  awd_ff=0;   awd_ff2=0;  end  else  begin  awd_ff<=awd;   awd_ff2<=awd_ff;   end  end  AWD is a input to the FPGA, and I'm just flopping it twice before I use it. The second register, awd_ff2, has the SDATA wired but not D data input. The first register has the "normal" wiring with D data input wired, nothing to SDATA, SCLR, or SLOAD.  Thanks in advance for any explanation of the differences between the two styles that DFFEAS can be wired, and/or what I'm doing wrong in Verilog.

[Altera_Forum]

By coming in through the D or SDATA, the router has multiple "choices" to get into the FF. If they both satisfy the design, i.e. make the connection and make timing, I believe the router can do either and it adds flexibility. I've had problems trying to script ECOs because of this, because on one compile it may use the D, another the SDATA, another it may go through the LUT as a pass-thru. None of these are wrong though.