Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20756 Discussions

DMA doesn't write due to high write waitrequest

Altera_Forum
Honored Contributor II
‎06-15-2008 07:13 PM
1,024 Views

I have an SOPC builder system that implements the design sample in ug_pci_express.pdf but with a different BAR setup and address bases. I've modified the testbench to reflect this, however I'm running into a weird issue: 

 

In dma_ctrl, the commands are received for the dma transfer and the read starts (successfully, getting the data). However, the write_waitrequest is always asserted, thus the write never starts. 

 

Any ideas? 

 

I attached a screenshot of the sopc builder with the connections and address offsets, and the modified bfm driver for the testbench. 

 

Thanks, 

Richard
multiple-attachments.zip
0 Kudos

Link Copied

1 Reply
Altera_Forum
Honored Contributor II
‎07-10-2008 06:27 AM
242 Views

If you show your codes about the DMA transfer, maybe I can help you to find the problem

0 Kudos
Copy link
Reply

Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.