Error (209048) during flash programming with PFL

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SW: Quartus Prime 16.0 SP2 

Cable: USB Blaster Rev.B CPLD: EPM1270T144C5 Flash: Intel StrataFlash PC48F4400P0VB0EE   Flash erase & programming pass with success. Verfication fails.   Messages (Program & Verify options are set in Programmer): ------------------------------------------------------------------------------ ... Info (209005): Programming status: programming flash memory at byte address 0x02A70000 Info (209005): Programming status: programming flash memory at byte address 0x02A80000 Info (209005): Programming status: verify on flash device 1 (Intel 28F512P30 Bottom Boot) at device chain position 1 Info (209021): Performing CRC verification on device(s) Error (209048): Verify (Block 0x00020000-0x00020800) failure on device number 1 Error (209012): Operation failed ------------------------------------------------------------------------------ Failure address can be 0x00020000-0x00020800 or 0x00020800-0x00021000 It may change after another programming procedure.   However verification of OPTION_BITS only is always successful. ------------------------------------------------------------------------------ Info (209006): Device 1 CFI Flash 1 is Intel 28F512P30 Bottom Boot (16 bits data bus) Info (209005): Programming status: verify on flash device 1 (Intel 28F512P30 Bottom Boot) at device chain position 1 Info (209021): Performing CRC verification on device(s) Info (209005): Programming status: verify on flash device 1 (Intel 28F512P30 Bottom Boot) at device chain position 1 is successful Info (209011): Successfully performed operation(s) ------------------------------------------------------------------------------   Flash and I/O power is OK.   1. There are several P30 parts with different timings: 100/110ns and 85/88ns.  Program and Erase Characteristics are different as well. But Manufacturer & Device ID Codes are exactly the same for all of the devices.   Can it possible be that Quartus takes parameters from the fastest device? So slower devices do not operate properly.  2. PFL was generated with "Flash Programming" option only. .sdc file was not specified.  All constraints that could be set are "set_false_path" according to PFL UG for asyncronous mode (Table 7). I decided not to set them at all. Am I wrong and some constraints must be set?  Previous board with EPM570 and the same flash device, power and pinout scheme worked fine. Q11.1 was used.