Gate level simulation of clock-less design

[Altera_Forum]

I implement logic designs without clocks, which are non-deterministic systems for research purposes. Do you know if Gate Level Simulation with ModelSim is suitable for clock-less designs? 

 For example, the following design oscillates when implemented on the FPGA. Can it be straightforwardly simulated with ModelSim Gate Level Simulation?  module main(SMA_CLKOUT); output SMA_CLKOUT; wire [2:0] inv /*synthesis keep*/; assign SMA_CLKOUT = inv[0];   assign inv[0] = ~inv[2]; assign inv[1] = ~inv[0]; assign inv[2] = ~inv[1];   endmodule   Thanks!

[Altera_Forum]

Yes, it should show what you want. Note the timing delays are not nominal, i.e. if using the slow timing model(which is the most common) then all delays will be the slowest possible. Hardware will probably run considerably faster. Depending on your goals, that may or may not be a problem. (I believe newer devices don't have gate-level sims either, so you have to target something older...)

[Altera_Forum]

Thanks Rysc! I am running the gate level simulation now. The problem is, though, that it gives me values of "x" because inv[2:0] is not initialized. But, "inv" is a wire, so I cannot initialize it. I am doubting if this kind of simulation is working for me.

[Altera_Forum]

It's a pure simulator problem, but you probably need to change the design style to allow an initialization. As another option, adding a reset signal to the chain (by a NAND or NOR gate in place of an inverter) doesn't change the LE delay.  

 I wonder which insights you expect from this trivial simulation setup? The "design" will work in real hardware as a ring oscillator, but the frequency is too high (about 1 GHz with Cyclone families, even more with faster series) to generate an output signal within the I/O standard specifications.

[Altera_Forum]

Thanks for the hint about the initialization! Now, however, ModelSim prompts an error after the reset signal goes down. 

The error is "Error: (vsim-3601) Iteration limit reached at time 50 ps," which is probably due to the closed loop that is not supposed to be in a regular design. FvM, you are right, a simulation based entirely on timing makes no sense for me. I thought that the gate level simulator is based on analog models for the gates, similar to a SPICE model. But, the simulation is only based on timing, right? Then, I need to try something else anyway.