Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Generating a new device tree blob.

Altera_Forum
Honored Contributor II
‎02-16-2014 11:35 PM
1,324 Views

The input files into the device tree generator are the following 

 

soc board xml file and the  

clocking xml file. 

 

My question is, are these files auto generated when the Quartus design is compiled -like the sopc info file or do i have to write them manually?  

 

I am trying to enable i2c1 on the hps and i am in the process of creating a new sd card image.
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Altera_Forum
Honored Contributor II
‎02-17-2014 09:35 AM
389 Views

I got my xml files together with GHRD (golden hardware reference example). Check for it on rocketboards.org.

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Altera_Forum
Honored Contributor II
‎02-17-2014 10:06 AM
389 Views

Hi  

 

Board info and clock info xml-s are a part of your board support package (included in GHRD) depends on your development board (they are different for Altera, Arrow-Terasic, EBV, Macnina boards). 

They haven't been automatically regenerated if you recompile your GHRD QSys design.  

 

See details: 

http://rocketboards.org/foswiki/documentation/gsrddevicetreegenerator 

 

 

Regards, 

 

Zs.V.
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