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I using HP ddr sdram module in my system,avalon bus work in 100M clk,ddr sdram also work in 100M clk,according to ddr sdram's element,it has 200M data bandwidth,but avalon bus only 100M clk,How to perform ddr sdram's 200M bandwidth?
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That's a system issue. When AVALON Master are connected to the memory controler, SOPC_BUILDER will add bunch of logic and then the timing path is quite significant. It's more true when your master is addressing many peripherals (Timer, Uart, Memory ctrl,...).
Under SOPC_BUILDER 7.2 you will find bridges (clock crossing, pipeline).
The first recommandation is to split low and high performance peripherals by using AVALON clock crossing. You can then create one single access point to the slow peripherals (UART, TIMER, PIO,...) and then the master will see only 2 acces points (memory controller, slow peripherals group).
The second help is to use the pipeline bridges to break down the timing path.
The last point is the targetted device. NiosII can run above 200MHz in a StratixII or III device, around 100MHz in CycloneIII.
Then, do not expect to have NiosII + DDR ctrl running at 200MHz in a CIII.
Maga
