How to save a 256kbyte samples with Arria II GX 190

[Altera_Forum]

Hi all, 

 I'm using an ArriaIIGX190 Device.   I have a design that recieves 8 channels to and I need to save from each channel 256Kbyte samples, meaning 2Mbyte samples for the whole design. I'm using a 125MHz clock. The ArriaIIGX190 doesn't have enough internal memory and I can't use an external memory (such as DDRIII) because the data rate is very high.   If someone have a solution for me, please reply me immediatly.   Thanks, Alon Goren, ELTA, IAI

[Altera_Forum]

--- Quote Start ---  and I can't use an external memory (such as DDRIII) because the data rate is very high  --- Quote End ---   Of course it's possible. 2 MByte is a rather small amount of data and can be handled most conveniently by SSRAM. But also DDR RAM operated at 300 MHz clock with a usual 64 Bit word width can basically handle the throughput. When writing full pages with sequential data, about 95% of the RAM speed are achievable as sustained rate. In any case, parallelization is the key.  You didn't mention the data word width, so I assumed up to 16 Bit for my calculation.  P.S.: DDR with 64Bit/200 MHz Clock can achieve already 3GByte/s, while your throughput would be only 2 GByte/s.

[Altera_Forum]

Dear Fvm, 

 Thank you for your quick replay. I forgat to mention that each channel is 32bit wide.   Alon Goren

[Altera_Forum]

You can calculate yourself, that a 64 Bit wide RAM at 300 MHz clock (600 MHz data rate) would be basically able to handle the data amount.

[Altera_Forum]

There are some more details I didn't mention before: 

1. The FPGA recieve the channels as DDR in 500Mbps (1Gbps data rate). 2. The ArriaIIGX190 (780 pins) has only 32 DQ/DQS or 16x3 DQ/DQS pins.   Thank you,   Alon Goren

[Altera_Forum]

The first point has no meaning for the storage method, I think. Intermediate data buffering (e.g. by a FIFO) would be necessary in most cases anyway.  

 I see, that it's difficult to connect the required memory with a 780 pin package (you also didn't mention this before). A 64 Bit DDR RAM would be ususally connected through x8 DQS groups, but it's not possible using one FPGA side, that has only 7 of it. Also other IO constraints have to be considered when selecting a suitable interface method, not known in detail.  Generally, DDR RAM offers the highest pin density in connecting external storage and also lowest relative cost. If it's not possible, you should check the SSRAM variant as well. If both fail, you need a larger package.