meaning of instructions

[Altera_Forum]

i'm a beginner in vhdl,so i have a program that i want to understand some instrunctions and functionalities.My program is:

PROCESS(clk, reset)

BEGIN

IF reset = '1' THEN

ready <= '1';

state <= TS2D_READY;

ELSE

IF clk'event AND clk = '1' THEN

CASE state IS

WHEN TS2D_READY =>

CASE ctrl_sig IS

WHEN Dwt2dCtrlVector(TCTRL_DWT2D_WIDTH) =>

width <= UNSIGNED(ctrl_data);

WHEN Dwt2dCtrlVector(TCTRL_DWT2D_HEIGHT) =>

height <= UNSIGNED(ctrl_data);

WHEN Dwt2dCtrlVector(TCTRL_DWT2D_TMP_DATA_OFFSET) =>

tmpDataOffset <= UNSIGNED(ctrl_data);

WHEN Dwt2dCtrlVector(TCTRL_DWT2D_LEVELS) =>

levels <= TO_INTEGER(UNSIGNED(ctrl_data));

state <= TS2D_INIT_HORIZ;

ready <= '0';

WHEN OTHERS =>

END CASE;

WHEN TS2D_INIT_HORIZ =>

src_cur <= (others => '0');

dst_cur <= (others => '0');

counter <= 0;

state <= TS2D_START_HORIZ; 

WHEN TS2D_START_HORIZ =>

CASE counter IS

WHEN 0 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_SRC_START_OFFSET);

dwt_ctrl_data <= STD_LOGIC_VECTOR(RESIZE(src_cur * CST_BUF_WIDTH, CST_CTRL_DATA_BUS_WIDTH));

WHEN 1 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_SRC_STEP);

dwt_ctrl_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(1, CST_CTRL_DATA_BUS_WIDTH));

WHEN 2 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_START_OFFSET_LO);

dwt_ctrl_data <= STD_LOGIC_VECTOR(RESIZE(dst_cur * CST_BUF_WIDTH + tmpDataOffset, CST_CTRL_DATA_BUS_WIDTH));

WHEN 3 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_START_OFFSET_HI);

dwt_ctrl_data <= STD_LOGIC_VECTOR(RESIZE(dst_cur * CST_BUF_WIDTH + SHIFT_RIGHT(width, 1) + tmpDataOffset, CST_CTRL_DATA_BUS_WIDTH));

WHEN 4 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_STEP_LO);

dwt_ctrl_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(1, CST_CTRL_DATA_BUS_WIDTH));

WHEN 5 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_STEP_HI);

dwt_ctrl_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(1, CST_CTRL_DATA_BUS_WIDTH));

WHEN 6 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_ELEM_COUNT);

dwt_ctrl_data <= STD_LOGIC_VECTOR(width);

WHEN 7 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_IGNORE);

state <= TS2D_CONTINUE_HORIZ;

WHEN OTHERS =>

END CASE;

counter <= counter + 1;

WHEN TS2D_CONTINUE_HORIZ =>

IF dwt_ready = '1' THEN

IF src_cur = height - 1 THEN

-----------

state <= TS2D_INIT_VERT;

----------- when testing horizontal pass only

-- state <= TS2D_TERMINATE;

ELSE

src_cur <= src_cur + 1;

dst_cur <= dst_cur + 1;

counter <= 0;

-- restart dwt

state <= TS2D_START_HORIZ;

END IF;

END IF;

WHEN TS2D_INIT_VERT =>

src_cur <= (others => '0');

dst_cur <= (others => '0');

counter <= 0;

state <= TS2D_START_VERT;

WHEN TS2D_START_VERT =>

CASE counter IS

WHEN 0 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_SRC_START_OFFSET);

dwt_ctrl_data <= STD_LOGIC_VECTOR(RESIZE(src_cur + tmpDataOffset, CST_CTRL_DATA_BUS_WIDTH));

WHEN 1 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_SRC_STEP);

dwt_ctrl_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(CST_BUF_WIDTH, CST_CTRL_DATA_BUS_WIDTH));

WHEN 2 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_START_OFFSET_LO);

dwt_ctrl_data <= STD_LOGIC_VECTOR(RESIZE(dst_cur, CST_CTRL_DATA_BUS_WIDTH));

WHEN 3 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_START_OFFSET_HI);

dwt_ctrl_data <= STD_LOGIC_VECTOR(RESIZE((dst_cur + SHIFT_RIGHT(height, 1) * CST_BUF_WIDTH), CST_CTRL_DATA_BUS_WIDTH));

WHEN 4 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_STEP_LO);

dwt_ctrl_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(CST_BUF_WIDTH, CST_CTRL_DATA_BUS_WIDTH));

WHEN 5 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_DST_STEP_HI);

dwt_ctrl_data <= STD_LOGIC_VECTOR(TO_UNSIGNED(CST_BUF_WIDTH, CST_CTRL_DATA_BUS_WIDTH));

WHEN 6 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_ELEM_COUNT);

dwt_ctrl_data <= STD_LOGIC_VECTOR(height);

WHEN 7 =>

dwt_ctrl_sig <= DwtCtrlVector(TCTRL_IGNORE);

state <= TS2D_CONTINUE_VERT;

WHEN OTHERS =>

END CASE;

counter <= counter + 1;

WHEN TS2D_CONTINUE_VERT =>

IF dwt_ready = '1' THEN

IF src_cur = width - 1 THEN

state <= TS2D_NEXT_LEVEL;

ELSE

src_cur <= src_cur + 1;

dst_cur <= dst_cur + 1;

counter <= 0;

-- restart dwt

state <= TS2D_START_VERT;

END IF;

END IF;

WHEN TS2D_NEXT_LEVEL =>

IF levels = 1 THEN

state <= TS2D_TERMINATE;

ELSE

width <= SHIFT_RIGHT(width, 1);

height <= SHIFT_RIGHT(height, 1);

levels <= levels - 1;

state <= TS2D_INIT_HORIZ; 

END IF;

WHEN TS2D_TERMINATE =>

ready <= '1';

state <= TS2D_READY;

END CASE;

END IF;

END IF;

END PROCESS;

-------->i want to know the meaning of instructions in gras.

Please help me

[Altera_Forum]

All of those are type conversions. It is really just a VHDL thing - it has no effect on the underlying hardware. 

 THe (others => '0') is just setting all bits in the bus to '0'