Importance of Impedance Matching

[Altera_Forum]

Hello, 

 I haven't done digital design since college and I'm still building up some general knowledge. Here's my situation:   I'm doing a design with the MAX II and I would like to use our in-house pcb milling machine for the board. The problem is that the thinnest blanks that our current setup can use have only 0.028" of dielectric between the two copper sides. I ran the numbers and figured that in order to make 50 ohm traces, they'd need to be ~53 mils wide, which is just impractical considering the pitch of the pins on the MAX II.    I'm trying to avoid ordering a 4 layer board from PCBexpress or somewhere similar. Is there any situation where impedance matched traces can just be ignored?    Also, what's the worst that could happen if I just ran 10 mil traces (which come out to about 107 ohms)?   I'm operating a 20 MHz clock with max I/O frequencies of 10 MHz. I'd be happy to provide any other information needed.     Thanks in advance, Jon

[Altera_Forum]

For clocked signals, I would just set the MAXII outputs to slow slew rate so they don't ring too much. At 20MHz, as long as your traces are not ridiculously long, they will settle before the next clock edge. 

 For asynchronous or clock signals, you should make sure the traces are properly terminated. For point to point signals, just put a series resistor at the driver such that the sum of the driver impedance and the resistor equals the trace impedance. For multidrop signals, run a single trace to all destinations. Parallel terminate the trace at or near the final destination.  Note that the above are general guidelines which should be followed regardless of trace impedance. There is nothing magic about 50 Ohm traces.

[Altera_Forum]

Honestly for what your doing you're probably fine. At 20MHz just use a low drive strength on the driver. 

 Please note that I do not give this advice as a general recommendation. The vast majority of the time, trace impedance is very important. Most of my boards have DDR2 and 3Gb serial channels. At 3Gb, even the tiniest mismatch in impedance impacts the signal.  But for what your doing, I think you'll be okay.  Jake

[Altera_Forum]

If your traces are long some cm don't worry about undesired effects, take care about setting low output driving current (about 4-5mA is OK) and put a series resistor of 22ohm on the clock trace. At your frequency it will be enough.

[Altera_Forum]

There's no particular reason to use 50 ohm traces to my opinion. Small traces are rather in the 80 to 90 ohm region, they can be operated impedance matched as well, if necessary. The suggestion to reduce the drive strength respectively using external series resistors are effectively achieving a source series termination, which is a good way for medium speed signals up to 100 MHz ore even more. 

 Driving an open end 90 ohm transmission line (you won't hardly achieve a higher impedance with your technique) with a 50 ohm source results in a +0.3 reflection factor and a maximal 30% overshoot. That's not a perfect signal quality, but would be sufficient to prevent damage of sensitive devices (e. g. Cyclone III) by overvoltages.

[Altera_Forum]

Just to chuck in my two pence worth as well - remember that it's the rise time of your signals (i.e. spectral contect) not the actual frequency of the signal which determines whether you need to do all of this. If your tracks are short relative to the rise time then you won't need to worry. If they are long then reducing the output drive (as previously suggested) will reduce the rise time and therefore enable you to drive longer track lengths. If you're worried then stick pads down on the PCB for some series resistors at the source end and tweak the values if necessary.

[Altera_Forum]

Thank you all very much for your replies. This thread has set me off on the right research track to answer many of my questions. As is often the case however, more questions did arise out the process.  

 I now understand digital signal integrity to be a process involving the following issues:    Impedance Matching  Transmission line parameters Ringing  Overshoot  Crosstalk  Skin Effect   And I've now got a decent handle on how all of these work and are related, with exception of ringing, which there doesn't seem to be a lot of consistant information online about as it pertains to digital systems. Anyone want to chime in?   Finally, many of the equations I've seen about signal integrity involves knowing the rise time of signals in order to determine their bandwidth, but the rise time of the MAX II and the oscillator I'm using (20 MHz) are not published. Altera stated the following in a white paper: The maximum rise and fall times for input signals are application dependent and vary based on the system and device noise and on the timing margins on the interface. Because of this dependency, Altera does not provide the maximum rise and fall time specifications for the following devices:   ■ Stratix® II, Stratix, and Stratix GX devices ■ Cyclone® II and Cyclone devices ■ HardCopy® series devices ■ APEX™ II and APEX 20K devices ■ MAX® II devices Anyone have a rule of thumb that they use or any insight to shed on the subject?     Thanks a million, Jon

[Altera_Forum]

Generally, you can expect that FPGA family output drivers (including MAX II) are fast enough to cause overshoot even on rather short, e.g. 2" or 50 mm traces. Adjusting the drive strength and - sometimes necessary - addig external series resistors can manage the issue.  

 Drive strength reduction can be seen as slowing down the edges in connection with the sum of load and pin capacitance or as adjusting a series source sided transmission line termination. For longer traces, the latter view gets physically evident to my opinion, although an additional capacitive load should be considered in an exact transmission line based analysis.  Beneath source sided termination, also load sided and any kind of hybrid termination is possible. A pure resistive load termination has the disadvantage of creatig high losses and is generally used only with high speed I/O standards. A RC load in contrast, causes some kind of complex mismatching, but can be adjusted for optimum pulse shape. Finally, if unmatched T connections respectively stubs are involved, smaller (a few 10 ohm) series resistors at the branch can at least reduce multiple reflections. They sometimes allow a fair signal quality with topologies, that should never exist following the transmission line theory.

[Altera_Forum]

Because rise/fall time is not a function of the driver but rather the entire circuit (taking in to account current strength, load capacitance, resistance, termination, etc.) you will not find it in a datasheet. 

 Once again, for what you are doing, you probably don't need to put so much effort into it. If your company has access to a board level simulation tool such as Mentor's Hyperlynx, that is an excellent way to simulate and visually see what effects the different components have on a circuit. You can actually lay out your trace with the CPLD pin and see what the signal looks like.  With regards to ringing. Usually ringing is an effect caused by the other issues (reflections due to impedance mismatch, improper terminations, improper trace layout, uncompensated inductance or capacitance, etc.) Actually in my experience the largest contributor to ringing is improper grounding. A weak current return path is guaranteed to give you ringing.  Jake

[Altera_Forum]

--- Quote Start ---    With regards to ringing. Usually ringing is an effect caused by the other issues (reflections due to impedance mismatch, improper terminations, improper trace layout, uncompensated inductance or capacitance, etc.) Actually in my experience the largest contributor to ringing is improper grounding. A weak current return path is guaranteed to give you ringing.   --- Quote End ---     Excellent description, thank you. I can now say that I understand what ringing looks like, how to prevent it, and what bad layout practices can lead to it.    What I don't understand is the physics behind it. I know that an impedance mismatch can cause it, but why? Is it something to do with reflections? Also, how does this explanation on Wikipedia fit in with the idea of ringing resulting from an impedance mismatch?     --- Quote Start ---    [...ringing] happens when an electrical pulse causes the parasitic capacitances (http://en.wikipedia.org/wiki/capacitor) and inductances (http://en.wikipedia.org/wiki/inductor)[citation needed (http://en.wikipedia.org/wiki/wikipedia:citation_needed)] in the circuit (i.e. those that are not part of the design, but just by-products of the materials used to construct the circuit) to resonate (http://en.wikipedia.org/wiki/resonance) at their characteristic frequency (http://en.wikipedia.org/wiki/frequency).   --- Quote End ---     Thanks again, Jon

[Altera_Forum]

Okay two separate things. 

 1 - Reflections - When a signal propagates along a transmission line of a certain impedance (this includes board traces) and encounters a change in impedance (this could be due to a change in trace width, a "T" in the line, a change in ground referencing, a pin on an IC, a pin on a discrete component, etc.), a portion of the energy in the signal is reflected back down the transmission line in the opposite direction. What doesn't get reflected, continues to propogate down the transmission line or lines. When that reflected portion of the signal reaches it's source or another impedance mismatch, the same thing will occur (part of the signal will reflect back in the original direction of the signal).  At the signal receiver, all of these reflections in combination with the original signal will add together either constructively or destructively depending on the point in time. This adding together of waves can be a cause of ringing.  2 - Ringing due to resonance.-Capacitive and Inductive sources within a circuit have a characteristic frequency. One way to think of this is like a pendulum or a swing. If you continue to push on the swing at the proper instance, the energy of your push will add to the energy of the swing and the swing will continue to gain energy and will swing higher and higher. The timing with witch you push on the swing is the swings characteristic frequency. This isn't a perfect analogy but it's the general idea. If you add energy to those sources of capacitance and inductance at the right frequency, they will resonate.  Typically, if ringing is due to a resonant circuit, it can be compensated for (this is what I meant by uncompensated capacitance and inductance). By compensating for the resonant circuit you will more than likely will make a tradeoff in the rise/fall times of the signal. You are essentially trying to filter out of the signal those frequency components that cause the resonance (which are at a higher frequency than your signal rate).  Another way to think of this would be to look at the circuit as a filter (that's what it is). Those capacitances and inductances in the circuit are poles and/or zeros in the transfer function of the filter. If the circuit is resonant, that means the filter has a low dampening effect at a specific frequency (It may even act as an amplifier at certain frequencies). You can change the filter's behavior by adding more poles/zeros to the transfer function (compensation).   Typically you compensate by adding more capacitive, resistive and/or inductive sources to the circuit.  Hope this helps. Maybe somebody else has something to add.  Jake