Measuring clock from DE0-Nano on scope

Altera_Forum · ‎05-19-2016

Hi,

I have a clock divider in my design, that takes the 50MHz clock in the DE0-Nano board and divides it so that I get 1MHz in it's output (I can't use a PLL since 50M to 1M is impossible).

Now I try to see the clock on a scope by connecting it to one of the GPIO pins but instead I get these weird signals that don't even resemble a square wave. I have no idea why since a few weeks ago it worked well for me. I tried connecting it to different pins on the GPIO (obviously not the VCC and GND)

The purpose of this test is to see that the clock output is indeed 1MHz because I need to interface with some servo actuator, and it has to be 1MHz precise.

Does anyone have any tips, or insights on why this is happening?

Thank you!

Altera_Forum · ‎05-19-2016

You need to be a lot more specific about your configuration. What type is the I/O port specified as? Ideally it is a CMOS output without an enable.

Is the clock signal you generate at all influenced by any other signals, such as a reset?

If you send the PLL clock output directly to a I/O pin to you see the correct clock signal?

Is your scope working? Ie, can you probe the 50MHz oscillator on the board and see the correct output?

The more information you can provide in your original question (including code snippets) the better, as followup posts like this aren't necessary.

Altera_Forum · ‎05-28-2016

Thanks for the reply and sorry for my late one.

Like I said, a few weeks ago it worked. A few hours after writing this post, it started working again, so I forgot about this thread.

To answer your questions:

1. According to the Quartus pin planner, it is LV-TTL 3.3V

2. Yes, a reset signal zeroes the clock signal. It is the only signal that has any effect.

3. Now, Yes. Before I did not. I should mention I do not see a clear square wave but I assume that's because 50MHz is too high for the scope.

4. It is working.

One important thing I should mention - the clock signal from my clock divider I'm seeing now has a low maximum voltage. The DE2 pins, as far as I know, should have an output of 5V (like the VCC) or at least 3.3V. Problem is that the clock signal has a maximum voltage of 1.5V barely. Any known issue that can cause this?

Also, the same clock signal that is the output of the divider is used to clock many modules. I heard that in the assignment editor you can tell the Quartus program that this is the case by assigning it as a global clock or something like that. Is it true, and if it is, what is the correct assignment?

Thanks!