Memory Collision between Nios II and HPS

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Memory Collision between Nios II and HPS

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Hi all,

I already refer the previous document and could create arch of NiosII and HPS on the CycloneV platform.

I also put the DMA controller, Address Expander and Pipeline bridge connect the f2h_sdram of HPS.

It is Fine that NiosII could Read/Write HPS' DDR via DMA, and HPS could also access the same memory.

Now, something occurs.

If NiosII still updates data of assigned memory area, Linux application on the HPS will get the old(same) data for a long time.

If changing the direction, Linux application on the HPS write the data to memory and the DMA of NiosII will not update data for several second.

I think this the data collision about NiosII and HPS access the same DDR memory of HPS.

Did anyone already solved this problem, or should I configure the parameter to avoid this issue?

Newbie Brian

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