Modify IP-CORE Ssram

[Altera_Forum]

Hello, 

 I'm trying to build a system in the SOPC-Builder with a Ssdram(Clock of whole system and components 100Mhz). The problem that I have is that running at 100 Mhz the IP-CORE of Ssram produces an error when I try to run in Nios II, I have run the same system with a 50Mhz clock.   I have tried to change a little the code for example introducing more wait times to read and write but I'm a bit lost, because I don't kwnow if I also have to change the archive.tcl or something else.    Thanks.   PD: I work with DE2-70 FPGA and sorry for my english

[Altera_Forum]

@vikonilov 

 The SSRAM on the DE2-70 is definitly fast enough for your 100MHz clock. I advise you to add a PLL for the SSRAM clock with a phase of about -3ns to compensate for the interconnect delay for getting of the Cyclone II chip to the SSRAM.   Hope this helps...

[Altera_Forum]

Thanks for the answer so quickly. 

 I kwnow that ssram supports 100Mhz and more frequency. The problem is that I have made a system running at 50Mhz and it goes, when I change to 100 Mhz in the Nios II appears an error telling me:" Verify failed between adress 0xXXXXX and 0xXXXXX".   Then I reviewed the verilog code that SOPC Builder has made of the Ssram component and I doubt if the wait of read and write are well made, because the structure is a state machine which depends of the clock. So if the clock changes maby these times change. I don't kwnow enough of verilog so I'm a bit lost with the archive name.v and the other archive name.tcl that goes with the component, that's why I ask for help.   I think that this is the problem, but maby(sure) I'm wrong, if anybody can suggest more ideas.   P.D Sanmao: I have introduce the clock with the phase(-3ns) and the error continuos the same.   Thanks a lot.