Multipoint LVDS backplane Bus using Stratix IV GT

[Altera_Forum]

Hi, 

 I am planning to design a multi lane Multipoint LVDS full duplex Bus to connect multiple Stratix IV GT FPGAs across multiple boards through the backplane using in-built LVDS transceivers. Maximum receivers connected to a Tx line are 24. Could there be any Fanout issues here?.   Thanks RK

[Altera_Forum]

Fanout isn't the right term, I think. Capacitive bus load can be an issue, however. Also achieving a minimum stub length will be essential. Did you review AN522?

[Altera_Forum]

--- Quote Start ---   I am planning to design a multi lane Multipoint LVDS full duplex Bus to connect multiple Stratix IV GT FPGAs across multiple boards through the backplane using in-built LVDS transceivers. Maximum receivers connected to a Tx line are 24. Could there be any Fanout issues here?.    --- Quote End ---  There are likely two issues you will face;  1. The LVDS buffers are not bidirectional, so you need to use both a transmitter LVDS pair, and a receiver LVDS pair. You can tie these together to make a potentially bidirectional LVDS signal, but  2. There is no tri-state control on the LVDS outputs, so you can not disable the transmitters without reconfiguring the FPGA.  This is the situation with the Stratix II FPGAs. I have not tested that this has changed on the Stratix IV, but I have not seen anything that indicates the LVDS design on the FPGAs has been changed.  You will not be able to implement full duplex using the LVDS on the FPGAs. If you absolutely have to implement this, since the backplane is already designed, you could use external LVDS transceivers from National Semiconductor and use FPGA single-ended I/O to communicate to the external LVDS transceiver.  Cheers, Dave

[Altera_Forum]

--- Quote Start ---  2. There is no tri-state control on the LVDS outputs, so you can not disable the transmitters without reconfiguring the FPGA.  This is the situation with the Stratix II FPGAs. I have not tested that this has changed on the Stratix IV, but I have not seen anything that indicates the LVDS design on the FPGAs has been changed.  --- Quote End ---    You better had read AN522 before writing this post. It's full title already suggests that the requested multipoint LVDS interface is well supported by Stratix IV:  "Implementing Bus LVDS Interface in Cyclone III, Stratix III, and stratix iv Devices"

[Altera_Forum]

--- Quote Start ---  You better had read AN522 before writing this post. It's full title already suggests that the requested multipoint LVDS interface is well supported by Stratix IV:  "Implementing Bus LVDS Interface in Cyclone III, Stratix III, and stratix iv Devices"  --- Quote End ---  Damn, how could you tell I didn't read it ... sheesh ...  So it appears the caveats with respect to LVDS have changed. The Altera LVDS transmitters with SERDES channels cannot be used for this application, because the transmitters can not be tri-stated.  Page 6:   --- Quote Start ---   DIFFIO_TX pin do not support true LVDS differential receivers.   --- Quote End ---  Page 4:   --- Quote Start ---   The BLVDS transmitter uses two single-ended (SE) output buffers with the second output buffer programmed as inverted.   --- Quote End ---  So what they've changed is you can use the single-ended transmit buffers in the LVDS receivers ... nice trick.  Previously you would have to emulate tri-stateable transmitters with external resistor termination networks (but then they could not operate at high bit-rates). I don't see any comments regarding the fact that these new transmitter buffers are current-output drivers, but its worth looking into it ... I'll have to try this out.   Thanks Frank!  Cheers, Dave

[Altera_Forum]

I must admit, that I didn't yet use the bus LVDS IO standard. But it's really interesting for a medium speed system bus in a 100 to 200, maximum 400 MBPS speed range.