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Number of reprogramming cycles

Altera_Forum
Honored Contributor II
‎02-26-2011 05:23 AM
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Hi, 

I am a beginner in using altera CPLDs. While going through the device handbook of MAX II and MAX V devices, I have seen that number of reprogramming cycles for these chips are limited to 100 cycles. Is it correct or not? Whether I will not be able to configure cpld for more than 100 times?? 

 

Xilinx and Lattice are supporting more than 10000 times. 

 

Thanks and Regards, 

Basil Alias
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Altera_Forum
Honored Contributor II
‎02-26-2011 09:07 AM
219 Views

 

--- Quote Start ---  

Is it correct or not? 

--- Quote End ---  

 

It's a specification. Semantically, it's incorrect, because the number 100 is written under "Maximum" cycles, so strictly spoken, no minimum is guaranteed. 

 

I would however expect a typical number of reprogamming cycles of 1000 or more. Practically, an issue could arise with development or prototype boards, because a production board won't be reprogrammed more frequently than a few ten times. 

 

With MAX V, the UFM part of the flash memory has got a 1000 cycles specification for the commercial grade.
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