PCIe to FIFO loopback

[Altera_Forum]

Hi  

I have reference design for PCIe loopback with onchip memory. This reference design is based on QSYS for CyclonelV GX.  Now i want to replace the on chip memory with a FIFO. Help me on this....

[Altera_Forum]

And? Where's the problem?

[Altera_Forum]

Basically i dont know how to start with... i have tried using on chip fifo and comparing the connections with that of on chip memory...i'm new to QSYS and trying to analyze the conenctions of PCIe core to onchip memory... i couldnt figure out how to replace the on chip memory withthat of on chip fifo...

[Altera_Forum]

Hi I have replaced the onchip memory with onchip fifo and have made connections as below (using QSYS).  

 fifo clk_in to pcie_hard_ip_0.pcie_core_clk fifo reset_in to clk_0.clk_reset fifo.in to dma_write_master_0.Data_Write_Master ffifo in_csr to pcie_hard_ip_0.bar1_0 fifo.out to dma_read_master_0.Data_Read_Master  I have assigned 0X07000000 to fifo_in  0X07000004 to fifo_out and  0X070000020 to in_csr.  do i have to modify any logic in Modular_DMA modules