Hi,
When i use Megewizard to generate DDR3 HMC(quartus II V13.0 and cyclone v device), there are many pll signals in the top module.
The EMI handbook says that are used for PLL sharing and "This interface is enabled only when you set PLL sharing mode to master or slave",but the setting is no sharing in my design.
How can i solve this problem?
//------------------------------------------------------------------------------------------------------
output wire pll_mem_clk, // pll_sharing.pll_mem_clk
output wire pll_write_clk, // .pll_write_clk
output wire pll_write_clk_pre_phy_clk, // .pll_write_clk_pre_phy_clk
output wire pll_addr_cmd_clk, // .pll_addr_cmd_clk
output wire pll_locked, // .pll_locked
output wire pll_avl_clk, // .pll_avl_clk
output wire pll_config_clk, // .pll_config_clk
output wire pll_mem_phy_clk, // .pll_mem_phy_clk
output wire afi_phy_clk, // .afi_phy_clk
output wire pll_avl_phy_clk // .pll_avl_phy_clk
//------------------------------------------------------------------------------------------------------
Best Regards
