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Valued Contributor III
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PS Configuration Using a MAX II Device

Altera has a white paper on how to use a MAX device to configure your FPGA in FPP, PS, PPA and Remote System Upgrade modes. 

 

http://www.altera.com/literature/wp/wp_max_flash.pdf 

 

This white paper assumes the FLASH memory used is parallel interface device of either 8 or 16 data bits wide. There is even source code available: 

 

http://www.altera.com/literature/wp/wp_max_flash.zip 

 

What I would like to do is configure my Stratix IV FPGA in PS mode using a MAX II device as the controller but use an EPCS128 serial FLASH as the FLASH device. I have not been able to find any information on the Altera site on how to do this other than this block diagram: Figure 10-10. 

 

http://www.altera.com/literature/handbooks/wwhelp/wwhimpl/js/html/wwhelp.htm#href=stx4_siv51010.13.0... 

 

Does anyone know where I can find more detail on how PS configuration using a MAX II device works? 

 

Thanks
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Valued Contributor III
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--- Quote Start ---  

 

Does anyone know where I can find more detail on how PS configuration using a MAX II device works? 

 

--- Quote End ---  

 

 

This should have what you need to know: 

 

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf 

 

Cheers, 

Dave
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Valued Contributor III
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The purpose of using a MAX II controller for PS configuration with serial flash isn't quite clear to me, because the serial flash can work in AS mode directly connected to the fPGA with less effort. 

 

The MAX II configuration controller reference design only supports parallel flash. You would need to design the serial flash interface yourself. I also doubt, that a MAX II with attached serial flash is supported by the Quartus programmer.
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Valued Contributor III
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Dave,  

Nice paper and thanks. 

 

FvM, 

I am looking at PS mode because of the configuration time boost. AS mode on Stratix IV runs somewhere between 17MHz to 40MHz. PS mode can run up to 125MHz. Because of design constraints, I cannot do FPP and my Nios II code will also be stored in this same FLASH chip. I agree that AS mode is much easier as it is direct connect no-brainer but the configuration time is just too slow. It's too bad that Altera does not allow for a pin to be driven by an external clock to be used as the AS DCLK.
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Valued Contributor III
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Hello, 

 

I understand your motivation. But besides modifying the MAX II PFL design, you'll most likely need to write your own virtual JTAG programming tool, because the Quartus programmer only supports parallel flash devices for "attachment". The interface between programmer and PFL is rather low level, directly performing flash programming commands that are different from serial flash commands.
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Valued Contributor III
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I'll give it a good read. http://www.qhd95598.com.cn/us.jpg

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Valued Contributor III
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--- Quote Start ---  

Hello, 

 

I understand your motivation. But besides modifying the MAX II PFL design, you'll most likely need to write your own virtual JTAG programming tool, because the Quartus programmer only supports parallel flash devices for "attachment". The interface between programmer and PFL is rather low level, directly performing flash programming commands that are different from serial flash commands. 

--- Quote End ---  

 

 

dear FVM 

could we let the FPGA update the configure file by itself?
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Valued Contributor III
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--- Quote Start ---  

could we let the FPGA update the configure file by itself? 

--- Quote End ---  

 

 

Yes. Once you have an FPGA image programmed into your flash and that FPGA configures correctly, the logic within the FPGA can allow reprogramming of the flash. If you want to be safe, you can create a MAX II controller that checks for multiple images. If you are programming in AS mode, then the serial flash is directly connected to the FPGA EPCS interface, but you can still reprogram it (and you can use multiple images). 

 

Cheers, 

Dave
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Valued Contributor III
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HI 

an FPGA image ? do you mean RPD file? 

but i don't know how to transmit the .rpd file data to FPGA ! 

could you show me the way?
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Valued Contributor III
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--- Quote Start ---  

 

an FPGA image ? do you mean RPD file? 

but i don't know how to transmit the .rpd file data to FPGA ! 

could you show me the way? 

--- Quote End ---  

 

 

There are many formats for FPGA configuration files, .rpd is one of them. The method to program it to your board is dependent on your board design. 

 

Are you using an evaluation kit or a board you designed yourself? 

 

Cheers, 

Dave
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Valued Contributor III
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--- Quote Start ---  

There are many formats for FPGA configuration files, .rpd is one of them. The method to program it to your board is dependent on your board design. 

 

Are you using an evaluation kit or a board you designed yourself? 

 

Cheers, 

Dave 

--- Quote End ---  

 

 

a board of myself! 

thanks for your reply!i have know to transmit the .rpd file data to FPGA by itself。 

 

but i don't know why rbf was different with rpd! 

 

but
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Valued Contributor III
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--- Quote Start ---  

 

a board of myself! 

i have know to transmit the .rpd file data to FPGA by itself。 

 

--- Quote End ---  

 

 

If you designed the board, then you should know how to get the .rpd into the board. That is part of the design stage! 

 

 

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but i don't know why rbf was different with rpd! 

 

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Who knows or who cares? These formats are not documented. There are compressed versions and non-compressed versions. 

 

If you can configure a board via JTAG, and then program the flash with the same design using .rpd or .rbf (with the appropriate configuration data bytes reversed if programming serial flash) and the board configures Ok, then the format of the source files is irrelevant. 

 

What exactly are you having difficulty with? 

 

Cheers, 

Dave
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