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Problem in Altera's University SRAM Controller IP Core, solution provided

Altera_Forum
Honored Contributor II
‎05-10-2009 02:33 AM
1,054 Views

Hello,  

 

Recently I was trying to achieve SRAM (chip IS61LV25616, 10ns access time) reads at 100MHz on my DE1 board, using Altera's University SRAM Controller IP Core.  

I am using SRAM for rendering video data for VGA at 100MHz, and using NIOS for setting up the needed textures.  

Unfortunately, using the stock controller did not work until I changed a setting in the Altera_UP_Avalon_SRAM_hw.tcl file.  

 

For DE1 and DE2 boards, the following setting is used:  

set_interface_property avalon_sram_slave readWaitTime 0  

This line is invalid, and the read wait time should be set to atleast 10ns.  

 

With this change, I am now able to achieve SRAM reads at 100MHz.  

 

I have already sent a mail to Altera, so that they can fix this issue, and spare future users of this problem.  

 

Kind regards. 

 

Edit: I should have placed this post in the IP/University sub-forum, sorry for that.
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