Problem with IP Compiler for PCIe

[Altera_Forum]

Hello everyone! 

 I am new to HDL and have a problem with my work. I have Cyclone IV GX transceiver starter kit and wanted to test "SOPC Builder Design Example" from "IP Compiler for PCI Express User Guide".  I only changed PCI Express lanes to x1 and disabled "Test out witdh".  After finishing generating the SOPC bilder system I want to compile the design, but when the compilation starts the fitter a problem occurs:  Error (176205): Can't place 89 pins with 2.5 V I/O standard because Fitter has only 62 such free pins available for general purpose I/O placement  Error (176204): Can't place pins due to device constraints  Error (171000): Can't fit design in device  Error: Quartus II 32-bit Fitter was unsuccessful. 3 errors, 36 warnings  Now my question, when I look in the Pin Planer there are 40(!) test_in_pcie_compiler_0 pins. I guess they are the problem, but how do I delete them or even not initialize those pins?   ps.: FPGA: EP4CGX15BF14C8  Thanks for answers! Best regards RK

[Altera_Forum]

try to make those pins virtual pins firstly.

[Altera_Forum]

Even when I add the test pins to the assignment editor and set them virtual the same message occurs. Same when I set "Enabled" to "NO". :(

[Altera_Forum]

Then You're doing something wrong. Are You sure You've set the CORRECT pins as virtual pins?

[Altera_Forum]

i think Virtual Pins are only supported in Subscription Edition, so in Web Edition they may be ignored

[Altera_Forum]

So is there any option to avoid the creation of test_in pins? Because there is one to turn off the test_out pins.  

Or can I just delete/comment out the initialization of the pins?

[Altera_Forum]

i'm not sure if you can turn them off 

 for now, you could assign 1 input bit to the whole bus. that should keep it from optimizing anything out