Problem with JTAG

[Altera_Forum]

Hi, 

 I use an USB Blaster cable to program an EP3C25U256 an EPCS16 with quartus II web edition 11.1. First, I programmed several times without any problem and after a while, i received an error "can't acces JTAG chain". I changed FPGAs, but the same problem happen after a while.  Is there if someone could have an explanation, it will be very nice!  Thanks, Alexis

[Altera_Forum]

I would suggest to check the JTAG signals with an oscilloscope. You could have a borderline signal quality that degrades with temperature when the board heats up, for example. Is it a custom board or a development kit?

[Altera_Forum]

Thanks for reply, 

 It's a custom board! But , if the increasement of temperature is the problem when the temperature decreases, I could program it when it will be cooler but I can't! However, when I checked the circuit with a voltmeter, I could see a short-circuit between TDI and GND that's why I thought I make a bad handling, in a first time, but with 3 different custom boards, it's not possible (the 3 times, it happens the same problem).

[Altera_Forum]

A short circuit between TDI and GND could indicate another kind of fail, such as an ESD or overvoltage on the pin itself. How is the board JTAG interface designed? Is it a direct connection from the connector to the JTAG FPGA pins or is there a buffer between the two? What I/O voltage standard is used? Do you have protection diodes in parallel? 

Do you connect your board to the USB blaster in a lab with proper ESD protection? Try to earth both the board and the USB blaster gnd pin before you plug it in.

[Altera_Forum]

The last board I programmed had the problem yesterday, and I try to program it again this morning and it doesn't work. There is no buffer between FPGA and connector, the I/O voltage standard used is 2.5V and there is no protection diodes. Moreover, for the last board,each time, I connect the USB blaster wearing a wrist strap. I will try to earth the board and the USB blaster gnd.

[Altera_Forum]

Still "can't access JTAG chain" when I earth the board and the USB Blaster gnd!

[Altera_Forum]

I've just seen the "enable ISP real-time to allow background programming (for MAX II and MAX V devices)" was enable. May this option create some troubles in FPGA's Jtag pins?

[Altera_Forum]

No this shouldn't change anything. 

When I talked about earthing I meant with a working board. It it is indeed ESD of overvoltage on a pin, once the JTAG pin is short circuited there is nothing you can so, other than change the FPGA.  Could you look at the JTAG signals with a scope (on a working board)? Check especially the overshoot when transiting from a 0 to a 1. It should never exceed 4.1V IIRC.

[Altera_Forum]

I think you should first ensure that the USB-Bluster or other cable else OK, for example, change a board and go a test. Then test the pins of JTAG to make sure the signals is OK when running the JTAG.