Problem with verilog

Altera_Forum · ‎05-05-2010

First of all excuse my english (french guy)

Well i want to do something simple with quartus but it doesn't work!

the idea is the following one:

i have a counter "count", 2 clocks "CLK1" and "CLK2" and a button "Bu"

when Bu=0

count=count+1 at each posedge of a clock "CLK1"

when Bu=1

count=count+1 but on posedge of another clock CLK2 more rapid than CLK1

when Bu returns to 0, count increases at the rythme of CLK1

CLK1 pos pos pos

CLK2 pos pos pos pos pos pos pos pos pos pos pos

Bu 000000000000000000000000000011111111111000000000

count 0 1 2 3 4 5 6

Someone can help me?

Thanks

Altera_Forum · ‎05-05-2010

Typically it's not possible to use two clocks on a register.

You should solve it like this:

always(clk) begin

if (bu==0) begin

count <= count + 1'd1;

end else begin

count <= count + 5'd20;

end

Altera_Forum · ‎05-05-2010

Another method would be to use two counters for each clock domain. Then design a module to re sync the counter values to the same clock domain before adding them together to get the total count.