Qsys - Nios write to FIFO

[Altera_Forum]

Hello, 

In my design project, Nios needs to write to an external FIFO. I created a custom Avalon MM component for the purpose. When Nios write to the custom component, the design expects to see the signals at the output of the Nios core. https://www.alteraforum.com/forum/attachment.php?attachmentid=7813   Listed below is the VHDL code of the said custom Nios-FIFO interface: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY out_fifo_avalon_interface IS PORT (  clock, resetn : IN STD_LOGIC;  write, chipselect : IN STD_LOGIC;  writedata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);  out_fifo_clk_export, out_fifo_cs_export : out STD_LOGIC;  Q_export : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)  ); END out_fifo_avalon_interface;   ARCHITECTURE Structure OF out_fifo_avalon_interface IS BEGIN  out_fifo_clk_export <= clock;  out_fifo_cs_export <= chipselect;  Q_export <= writedata; END Structure;  The project compiled ok (no hard errors). However, when Nios write to FIFO interface MM address, chipselect and clock are nowhere to be seen on the scope. Could someone help? Thanks.

[Altera_Forum]

Are you sure the CPU is writing at the correct address?

[Altera_Forum]

Thank you, Daixiwen, for the reply. I thought I was writing to the correct address. But, since you asked, I am not positive any more. Something weird happens in EDS software side that I cannot explain. 

 In my design, the base address of the out_fifo interface is defined as "#define OUT_FIFO_AVALON_INTERFACE_0_BASE 0x5060" in system.h. The data is byte wide. Therefore in sending the data to fifo, "*out_fifo=0xaa;" is used: where out_fifo is defined by "#define out_fifo (unsigned char *) OUT_FIFO_AVALON_INTERFACE_0_BASE". I think this part is probably okay.  The weird thing I am having on EDS is about symbol resolution. Even though OUT_FIFO_AVALON_INTERFACE_0_BASE is defined in system.h and the application c file does include the system.h file, EDS says "Symbol 'OUT_FIFO_AVALON_INTERFACE_0_BASE' could not be resolved". To keep going, I define out_fifo by "#define out_fifo (unsigned char *) 0x5060" in the local app file. In the same app file, the app program refer to other symbols defined in system.h without problems. I have not been able to figure out what is going on yet. Have you seen anything like that? Thanks

[Altera_Forum]

Still have not been able to figure out the cause of unresolved label issue in EDS software. Re-build the software project from ground up. The problem is no longer there. 

 The app software writes to FIFO at a constant interval. However, per the waveform on the scope, it looks as if FIFO was written to only once then the program quit writing. On advice, I wrote to 0x8000,5060 instead of 0x5060 to bypass cache. This last step appears to take care of the problem.

[Altera_Forum]

Its possible that Eclipse was trying to compile your project with an old version of the BSP that didn't have this component, and as a result didn't replace OUT_FIFO_AVALON_INTERFACE_0_BASE with the correct value. I don't use Eclipse that much so I don't know how smart it is when you partially recompile a project. 

As for your other line, it looks like you found the solution yourself ;). You should always bypass the cache when accessing a component, either by using the IORD/IOWR macros, or change the address pointer. For the latter you can either set bit 31, as you did, or use the alt_remap_uncached() function provided by Altera, which is a more portable solution.