Question about normal differential I/O input ports pairs to Cyclone 10 GX interconnection

[MinzhiWang]

Hello guys,

We are using 10CX220YF780E5G devices in our application. This FPGA mainly receive ADC output data by using LVDS differential pairs interface. I can find many posts here to discuss about this kind of application. And we learnt more about this here.

Now we have another question about LVDS interface, however, input sources are not from ADC. The sources are from several indempent pulse generators. Which generate pulse signals and feed them to FPGA thru CML standard. We connect these CML pairs to C10GX's LVDS pairs I/O pins with reasonable terminations. We have two questions here:

1. Do you have any material about CML to LVDS hardware inconnecting for us to refer?

2. How LVDS function inside FPGA logic to process this kind of pulse signal (not serail data input)? Or can the LVDS I/O pair process this kind of differential input siganl?

[FvM]

1. LVDS inputs are supporting Vicm downto 0V for speed upto 700 MBPS. Thus CML pair with resistive termination can directly drive LVDS input.
2. LVDS input can drive FPGA logic without restrictions. In contrast, Cyclone GX SERDES IO can only connect to LVDS IO standard.

[MinzhiWang]

Hello FvM,

Thanks for you reply.

Our hardware design as following images. The exteranl CML pair signal (CBA_Trigger pair) is connected to C10GX's LVDS pair input I/O after resistance&capacitance termination (Trigger pair). According to you reply, this can't be supported for Cyclone 10 GX Serdes I/O?

If this is the case, we have to use one CML to LVDS converter chip to translate the CML signal to LVDS signal, then connect the converted signal to Cyclone 10GX Serdes I/O. Am i right?

[MinzhiWang]

BTW, we don't want to use Serdes for this input pulse signal. We only want to implement internal simple logic to detect and check input square "pulse".

[AqidAyman_Intel]

Based on the pin connection guideline, the pin that you used to connect the Trigger_pair are the true LVDS receiver/transmitter channels.

Refer to this link: https://www.intel.com/content/www/us/en/docs/programmable/683417/current/differential-i-o-pins.html

[MinzhiWang]

Hello AqidAyman,

Are there any materials about how to connect CML pairs to FPGA lvds pairs?

[AqidAyman_Intel]

Hello,

I am not quite sure if we have specific documentation that talks about the CML to LVDS hardware interconnecting.

However, I found a documentation that mention the CML I/O standard assignment, but this is related to Stratix 10 transceiver L and H-tile.

https://www.intel.com/content/www/us/en/docs/programmable/683621/current/reference-clock-i-o-standard.html

[AqidAyman_Intel]

Hello,

I wish to follow up on this with you.

Did my last answer help you? Do you need more support?

Please let me know if you need more help.

Regards,

Aqid

[MinzhiWang]

Hello AqidAyman,

Thanks for you patience on this question.

I am asking the structure about interconnection between CML and LVDS. CML is dirver, and LVDS is receiver. In our case, the receiver is Cyclone 10 GX device. We use its LVDS I/O pairs as the receiver.

There are CML drivers outside of Cyclone 10 GX FPGA. These drivers need to be connected to FPGA. We connect them directly refer following description:

Intel FPGA has many LVDS receivers, so we think the external CML drivers can be fed into FPGA directly according to above image indication. BYW, there are two modes, AC coupling and DC coupling. Our hardware can implement these two modes.

So my question is that can C10GX devices LVDS receivers be used as above image's LVDS receivers? I just want to confirm with Intel engineer guys about this.

Thanks again.

[FvM]

Hi
applicable connection scheme depends on CML driver output common mode voltage. In case if doubt, the third scheme (AC coupling with bias voltage, Vbb = 1.2V) should be implemented.

[MinzhiWang]

Hi FvM,

Thanks for you reply, we'll test and verify the hardware firstly. I hope we can discuss more about C10GX devices here.

Hello AqidAyman,

I think you can close this thread now. 

[AqidAyman_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you.