RJ-45 Pins on Cyclone IV GX?

[Altera_Forum]

Hello, 

 Can anyone tell me the name of RJ-45 pins on Cyclone IV GX? I need to connect them to my project, but I don't know their name. :oops:

[Altera_Forum]

--- Quote Start ---  Hello,  Can anyone tell me the name of RJ-45 pins on Cyclone IV GX? I need to connect them to my project, but I don't know their name. :oops:  --- Quote End ---    Same answer as your last question:  http://www.alteraforum.com/forum/showthread.php?t=33852  You need to look at the schematic for your board.  Cheers, Dave

[Altera_Forum]

I found them in the schematic, but I don't see them in Pin Planner. :confused:

[Altera_Forum]

Because You didn't add those signals to the top level file.

[Altera_Forum]

--- Quote Start ---  I found them in the schematic, but I don't see them in Pin Planner. :confused:  --- Quote End ---    Pin planner will only show them if you have a design that uses them.  I typically have a top-level entity with all ports defined and then use a Tcl script to assign pins.  Using the GUI, I think you can elaborate the design (for Quartus to find out which pins you have used), and then you can use the Pin Planner to assign the pins per the schematic.  Cheers, Dave

[Altera_Forum]

I guess I'd better try to use Tcl script to assign pins. Can you please give me a Verilog example that assign a port to pin 1 of RJ-45 as given schematic below? 

 http://img849.imageshack.us/img849/7372/101001000.png

[Altera_Forum]

--- Quote Start ---  I guess I'd better try to use Tcl script to assign pins. Can you please give me a Verilog example that assign a port to pin 1 of RJ-45 as given schematic below?   --- Quote End ---    You cannot assign an FPGA pin to the RJ-45, since the FPGA does not have any connections to the RJ-45 - look at the schematic!  The FPGA connects to the PHY (Physical Layer chip). The PHY is a Marvel 88E1111 device. Marvel require a non-disclosure agreement (NDA) to view the data sheet for this part.   The FPGA needs to instantiate a controller to communicate with the ethernet PHY. I believe its called something like the Altera Triple Speed Ethernet (TSE) IP core.   Cheers, Dave

[Altera_Forum]

So, TSE is the only way to transfer data between FPGA and RJ-45 port? :)

[Altera_Forum]

--- Quote Start ---  So, TSE is the only way to transfer data between FPGA and RJ-45 port? :)  --- Quote End ---    An ethernet IP core is the only way. The Altera TSE just happens to be one implementation. Opencores.org might have another.  Cheers, Dave