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Register Bank Simulation Failure on DE2

Altera_Forum
Honored Contributor II
‎12-20-2011 06:23 PM
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I'm having trouble trying to simulate a register bank on DE2 using verilog HDL, if i put the wrinting section plus the reading section together, the initial values are totally ignored and they start at random values, but that does not occur when it's just one or another, and if i include the reset section the code doesn't compile at all. I'm sending attached a simplified version of the code, if anyone knows what's wrong or figure out how to solve this let me know. 

 

Thanks!
test.v
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