SoC Cyclone V example design : error->hierarchical path is too long

[Altera_Forum]

Hello Friends, 

 I have altera SoC Cyclone V Board, and i am trying to understand the board using its gsrd located at "altera/Q13.1/embedded/example/hardware" . this design example is came along with quartus13.1 tool.  1. while compiling this design my Quartus 13.1 (Full Version) generate an error saying hierarchical path is too lonng  2. then copy paste this project to d drive and recompile the project again it generate the same error. 3. Rename the project name with small name like SoCV but again it generate the same error.   * For Reference, i have attached the print-screen of my project.  Is any thing i am missing please point out  *my machine having windows-7

[Altera_Forum]

A couple of questions: 

 1) Do you have a C: drive? If so does this happen when the project is opened there? 2) Is your Windows D: drive a mapped network drive?  As far as I know neither of those should matter but I'm wondering if you are running into a corner case.  Also can you attach the full report .txt file from your compilation? There might be something else happening earlier in the compile causing the tools to think that your hierarchical path is too long. The way I interpret that message is that the hiearchy in the design itself is too deep which should be independent of the files on the file system. The only way to affect the design heirarchy is to modify the design, so is this the vanilla GSRD that you are trying to compile after re-generating the system in Qsys?

[Altera_Forum]

Thanking you for reply, 

1. Yes i have tried it on C: drive also but result will remain same (having hierarchical path is too long error) 2. no my windows D: drive is not mapped with network  attached:- 1. I have attached my sourc project "CVSoC_ghrd" which i have taken from c:\altera\q13.1\embeded\example\hardware\cvsoc_devkit_ghrd 2. i have attached my current working project "CVSoc_ghrd. 3. Print short of path path source and current working directory  regards  kaushal

[Altera_Forum]

I recreated this on my side. I'm not sure how this happened but it's a valid error because when I look at the heirarchy it's ghrd_top --> soc_system:soc_inst --> ghrd_top --> etc... (just keeps repeating). 

 The issue seems to be the top level file instantiates soc_system which then instantiates the top level file which causes this vicious looping to occur. Did you modify the project since it looks like a human caused this and not the tools?

[Altera_Forum]

Not exactly modify, i just create the symbol from ghrd_top.v 

 1. File-->Create/Update ---> Create Symbol file for Current File (ghrd_top.v) 2. File--> New File 3. Add the newel Created symbol (soc_system.bdf)-->add input and output port 4. Set as Top Level Entity 5. then Start Compilation  ------------------------------------------------ if Once Again i remove the soc_system.bdf from project and recompile---> compile successfully

[Altera_Forum]

The problem is ghrd_top.v is still the top level in your design (double click it in the heirachy and that's the file that loads). It then instantiates soc_system.bdf but that instantiates ghrd_top.v which is causing the loop. 

 I think you are confusing symbols and schematics. Symbols are the blocks that show up in the schematic which is described by the .bdf file. I think what you really want to do is enable the symbol generation for the Qsys system, then include that symbol into a larger schematic that includes all the other stuff that's in ghrd_top.v You would make this new schematic the top level of your design instead of ghrd_top.v

[RVran]

Try to use Long Path Tool, it really can help you with that.