Stratix IV FF Sync V/s Async Clear

[Altera_Forum]

Is there any distinct disadvantage to using the synchronous clear in the Flip/Flops in 

Stratix IV (like restricted no. per LAB or using more logic or slower timing etc?) versus using the async. clear. I have a choice of using either in my design. But reading Rysc's excellent timequest user guide, I came across the lines  "But the second reason for using an asynchronous reset is that it gets better results in Altera FPGAs. There is a dedicated asynchronous set/reset on each register, and if the design doesn’t use them, they are wasted. More importantly, if the reset is synchronous, it will use up synchronous inputs, whether it be the synchronous clear port or an input to the LUT, that could have been used for general logic. So making the domain-wide reset synchronous will make the design a little larger and a little slower."  Is this still true for Stratix IV and above.

[Altera_Forum]

Yes.  

One thing I like to look at is the Fitter Report -> Resource Utilization -> Control Signals. I then sort on the Usage column. You may code your reset for the asynchronous clear, but you'll see the design is full of synchronous clears too. This means synthesize was able to take your general RTL and target the synchronous clear port of the register/s, thereby making a more optimal area and performance design. The difference isn't huge, but it's not in the noise either. (It's also interesting to look at clock enables, as most designs have a ton that were never explicitly coded for)

[Altera_Forum]

Many thanks. If I understand you correctly, what you are saying is that 

If I use only async. clear, then the synthesizer has room to remodel some as sync.clears and there by optimize some parameter. Whereas If I model using synch.clear  then it takes away the room for such play. There is no other disadvantage to using synch. clears such as more LUT logic or inputs since they seem to be native to the FF and not modeled using LUT resources.  I hope my understanding is correct.

[Altera_Forum]

Sounds right. Synchronous clears and asynchronous clears are both lab-wide signals, so you can't pack a lot of different ones into a LAB, but since we're talking about your domain-wide reset, that shouldn't be a problem at all.

[Altera_Forum]

Besides better resource utilization, there are other reasons to use the asynchronous clear (with synchronized release) as the system wide reset. 

- it's the only means to achieve defined output states before the clock is running - built-in resources like PLLs or Altera IP are relying on asynchronous reset

[Altera_Forum]

Many thanks for such detailed replies!