Hi Folks,
I am using a Cyclone III EP3C10. In my design I have an altlvds_rx module being fed from a 40MHz clock. I also have an altpll generating three clocks from a 50MHz base clock. The LVDS is using is generating its own PLL to get a 200MHz data clock from the frame clock. The altpll is generating 100MHz, 40MHz and 200MHz from its base clock.
When I open timing analyzer and derive pll clocks the 200MHz altpll clock out is not shown, is this because it is optimizing the design and using the 200MHz clock being generated by the altlvds for anything that uses the altpll 200MHz?, all the other clocks seem to be present and correct!
Thanks for any advice you can offer.
D
