Timing Constraint problem on set_input_delay for Video LVDS Rx

[Altera_Forum]

Hi,I encountered another problem. 

If a input signal is data and also clock,like LVDS transceiver for video,then there is a problem. create_clock -add -name {Ext_LVDSClkA} -period 16.666 -waveform {0 9.523} [get_ports {LVDS_CK}] create_clock -add -name {Ext_LVDS_fast_ClkA} -period 4.761 -waveform {0 2.380} create_generated_clock -name {Int_PCLKA} -divide_by 1 -multiply_by 1 -phase 0 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated| pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated |pll1|clk[0]}] -add create_generated_clock -name {Int_PCLKA_2X} -divide_by 1 -multiply_by 2 -phase 0 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated| pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated |pll1|clk[1]}] -add create_generated_clock -name {Int_IOCLKA} -divide_by 2 -multiply_by 7 -phase 56.25 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated| pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated |pll1|clk[2]}] -add set tCO_max 0.5 set tCO_min -0.2 set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -max [expr $tCO_max] [get_ports {LVDS_DT [*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -min [expr $tCO_min] [get_ports {LVDS_DT [*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -clock_fall -max [expr $tCO_max] [get_ports {LVDS_DT [*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -clock_fall -min [expr $tCO_min] [get_ports {LVDS_DT [*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -max [expr $tCO_max] [get_ports {LVDS_CK}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -min [expr $tCO_min] [get_ports {LVDS_CK}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -clock_fall -max [expr $tCO_max] [get_ports {LVDS_CK}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDS_fast_ClkA}] -clock_fall -min [expr $tCO_min] [get_ports {LVDS_CK}]   set_false_path -setup -rise_from [get_clocks {Ext_LVDS_fast_ClkA}] -rise_to [get_clocks {Int_IOCLKA}] set_false_path -setup -fall_from [get_clocks {Ext_LVDS_fast_ClkA}] -fall_to [get_clocks {Int_IOCLKA}]   set_false_path -hold -rise_from [get_clocks {Ext_LVDS_fast_ClkA}] -fall_to [get_clocks {Int_IOCLKA}] set_false_path -hold -fall_from [get_clocks {Ext_LVDS_fast_ClkA}] -rise_to [get_clocks {Int_IOCLKA}]   set_multicycle_path -end -hold -from [get_clocks {Ext_LVDS_fast_ClkA}] -to [get_clocks {Int_IOCLKA}] -1 set_multicycle_path -end -setup -from [get_clocks {Ext_LVDS_fast_ClkA}] -to [get_clocks {Int_IOCLKA}] 1  Is there any problem on my above timing constraint? And, In the TimeQuest Timing Analyzer tool,the launch clock of LVDS_A_CK is Ext_LVDSClkA not Ext_LVDS_fast_ClkA.I don't know why the launch clock is not Ext_LVDS_fast_ClkA.

[Altera_Forum]

I modifyed my constraint as follows. 

create_clock -add -name {Ext_LVDSClkA} -period 15.384 -waveform {0 8.790} [get_ports {LVDS_A_CK}] create_generated_clock -name {Int_PCLKA} -divide_by 1 -multiply_by 1 -duty_cycle 50 -phase 0 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[0]}] -add create_generated_clock -name {Int_PCLKA_2X} -divide_by 1 -multiply_by 2 -duty_cycle 50 -phase 0 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[1]}] -add # #create_generated_clock -name {Int_IOCLKA} -divide_by 2 -multiply_by 7 -duty_cycle 50 -phase 78.75 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[2]}] -add create_generated_clock -name {Int_IOCLKA} -divide_by 2 -multiply_by 7 -duty_cycle 50 -phase 56.25 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[2]}] -add set LVDSA_tCO_max 0.5 set LVDSA_tCO_min -0.5  set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -max [expr $LVDSA_tCO_max] [get_ports {LVDS_A_CK}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -min [expr $LVDSA_tCO_min] [get_ports {LVDS_A_CK}]  set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -max [expr $LVDSA_tCO_max + 2.197] [get_ports {LVDS_A_D[*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -min [expr $LVDSA_tCO_min + 2.197] [get_ports {LVDS_A_D[*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -clock_fall -max [expr $LVDSA_tCO_max + 2.197] [get_ports {LVDS_A_D[*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -clock_fall -min [expr $LVDSA_tCO_min + 2.197] [get_ports {LVDS_A_D[*]}]  set_multicycle_path -setup -rise_from [get_clocks {Ext_LVDSClkA}] -fall_to [get_clocks {Int_IOCLKA}] -end 2 set_multicycle_path -setup -fall_from [get_clocks {Ext_LVDSClkA}] -fall_to [get_clocks {Int_IOCLKA}] -end 2 set_multicycle_path -setup -rise_from [get_clocks {Ext_LVDSClkA}] -rise_to [get_clocks {Int_IOCLKA}] -end 2 set_multicycle_path -setup -fall_from [get_clocks {Ext_LVDSClkA}] -rise_to [get_clocks {Int_IOCLKA}] -end 2 # ##set_multicycle_path -setup -rise_from [get_clocks {Ext_LVDSClkA}] -through [get_pins {*u_lvds_rx0|r_LVDSClk[0]|d}] -rise_to [get_clocks {Int_IOCLKA}] -end 1 # ##set_multicycle_path -setup -fall_from [get_clocks {Ext_LVDSClkA}] -through [get_pins {*u_lvds_rx0|r_LVDSClk[0]|d}] -rise_to [get_clocks {Int_IOCLKA}] -end 1 # #set_multicycle_path -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} -setup -end 1 # #set_multicycle_path -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} -hold -end 0 set_max_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 0.686 + 2.197] set_min_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 0.686 - 2.197] I found that it is hard to meet the timing for clock skew of setup and hold differ big(difference is about 0.5ns).For this case,what ways are there? And I have no confidence on my constraint,is there any problem in my constraint?

[Altera_Forum]

I modifyed my constraint as follows. 

create_clock -add -name {Ext_LVDSClkA} -period 15.384 -waveform {0 8.790} [get_ports {LVDS_A_CK}] create_generated_clock -name {Int_PCLKA} -divide_by 1 -multiply_by 1 -duty_cycle 50 -phase 0 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[0]}] -add create_generated_clock -name {Int_PCLKA_2X} -divide_by 1 -multiply_by 2 -duty_cycle 50 -phase 0 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[1]}] -add # #create_generated_clock -name {Int_IOCLKA} -divide_by 2 -multiply_by 7 -duty_cycle 50 -phase 78.75 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[2]}] -add create_generated_clock -name {Int_IOCLKA} -divide_by 2 -multiply_by 7 -duty_cycle 50 -phase 56.25 -source [get_pins u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|inclk[0]] [get_pins {u_ClkGen|u_Rx0PLL|altpll_component|auto_generated|pll1|clk[2]}] -add set LVDSA_tCO_max 0.5 set LVDSA_tCO_min -0.5  set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -max [expr $LVDSA_tCO_max] [get_ports {LVDS_A_CK}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -min [expr $LVDSA_tCO_min] [get_ports {LVDS_A_CK}]  set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -max [expr $LVDSA_tCO_max + 2.197] [get_ports {LVDS_A_D[*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -min [expr $LVDSA_tCO_min + 2.197] [get_ports {LVDS_A_D[*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -clock_fall -max [expr $LVDSA_tCO_max + 2.197] [get_ports {LVDS_A_D[*]}] set_input_delay -add_delay -clock [get_clocks {Ext_LVDSClkA}] -clock_fall -min [expr $LVDSA_tCO_min + 2.197] [get_ports {LVDS_A_D[*]}]  set_multicycle_path -setup -rise_from [get_clocks {Ext_LVDSClkA}] -fall_to [get_clocks {Int_IOCLKA}] -end 2 set_multicycle_path -setup -fall_from [get_clocks {Ext_LVDSClkA}] -fall_to [get_clocks {Int_IOCLKA}] -end 2 set_multicycle_path -setup -rise_from [get_clocks {Ext_LVDSClkA}] -rise_to [get_clocks {Int_IOCLKA}] -end 2 set_multicycle_path -setup -fall_from [get_clocks {Ext_LVDSClkA}] -rise_to [get_clocks {Int_IOCLKA}] -end 2 # ##set_multicycle_path -setup -rise_from [get_clocks {Ext_LVDSClkA}] -through [get_pins {*u_lvds_rx0|r_LVDSClk[0]|d}] -rise_to [get_clocks {Int_IOCLKA}] -end 1 # ##set_multicycle_path -setup -fall_from [get_clocks {Ext_LVDSClkA}] -through [get_pins {*u_lvds_rx0|r_LVDSClk[0]|d}] -rise_to [get_clocks {Int_IOCLKA}] -end 1 # #set_multicycle_path -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} -setup -end 1 # #set_multicycle_path -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} -hold -end 0 set_max_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 0.686 + 2.197] set_min_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 0.686 - 2.197] I found that it is hard to meet the timing for clock skew of setup and hold differ big(difference is about 0.5ns).For this case,what ways are there? And I have no confidence on my constraint,is there any problem in my constraint?

[Altera_Forum]

I want to capture the LVDS_A_CK with the clock INT_IOCLKA generated by PLL following the timing in the visio.So I do the timing constraints as follows. 

set_max_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 1.099 + 2.197] set_min_delay -from {LVDS_A_CK} -to {LVDSRxTop:u_LVDSRxTop|lvds_rx:u_lvds_rx0|r_LVDSClk[0]} [expr 1.099 - 2.197] 2.197 is the half of Cycle of INT_IOCLKA,and 1.099 is the shift phase value of INT_IOCLKA. Are the timing constraints right?