Timing Simulation with Altera-Modelsim

[Altera_Forum]

Hello to all, 

I'm new at working on CPLD in VHDL. Fortunately, I knew this language from University and I can understand and write it quite well. Maybe, the greatest difficulties are the settings of the softwares. I use Quartus II 9.1 SP2 and Altera-Modelsim 6.5b.   I made a project about a PWM. I also made a testbench for the Functional Simulation and it works quite well. Now, I would like to learn to do the Timing Simulation, but I can't understand how to do it.   I know that I need two files: the netlist (.vho) and the .sdo file. In some way, I could obtain these files (in EDA Tool Settings, under Timing Analysis, I choose "Custom" with Format to Output Netlist "VHDL").   Now I have to use them in Modelsim. I could understand that: 1) In the library work of the project, I have to compile the vho file; 2) In the Simulation menu, I choose "Start simulation", on the tab "SDF" I open my .sdo file 3) In the "Start simulation" window again, on the tab design, I choose my top entity (not the testbench)   The simulation is ready to start, but there isn't any clock or stimulus to simulate...this is easy to understand, because in the functional simulation, that information were in the testbench... But if I choose the testbench instead of the top entity in point 3), the vsim tells me errors about "No default binding for components"...   My questions: A) am I doing anything wrong or this way is right? B) have I got to set my stimuli in the .vho file? and in this case how? C) what about .sdf max, min, latest? I understand that they are like constraints, so my simulation can tell me if they are not met, is it right? and how to set them? D) it is important to set "Apply to Region" field in my point 2)? what is to be set there? the top level entity? in which format? E) philosophically, is it important to do timing simulation if timing requirements are already met in classic time analyzer on Quartus II? (I set a Fmax of 100 Mhz) F) this is a little off topic: why if I use Time Quest instead of Classic Time Analyzer, the requirement about the Fmax isn't met? (it tells me a Fmax of about 94 Mhz)   Thank you for the patience and the disponibility :)    ps: the device I use is from Max II family, if this can be useful.

[Altera_Forum]

your timing/gate level simulation should also have a test bench which instantiates the gate level netlist of your project. the idea is basically the same as RTL simulation, except all of your HDL is compiled into a single HDL netlist which is the .v(h)o file.

[Altera_Forum]

Hello thepancake, thank you for the reply. 

 After many trials I was able to start simulation, and this was slower than normal, so I thought I was right. But the behaviour was the same of functional simulation, and I know that it can't be, because timing simulation in Quartus told me a wrong timing behaviour, different from the functional.   I must be wrong. I understand your advice. So have I to write a new testbench for gate level netlist? The vho has the same declaration of my top-level entity, except for generic constants' declaration.... Or maybe I have to do a new library, where I put only my new testbench and the vho instead of the top-level entity file???  Because when I compile vho, it puts a new architecture to my top-level entity, which now has 2 architectures...maybe I am wrong here!

[Altera_Forum]

a timing simulation will execute much slower than an RTL simulation. its possible that your timing simulation results will match RTL simulation results, even if static timing is not met. the stimulus to your design under test hasn't exercised the worst case path that timing analysis flagged. 

 you shouldn't have to make a new test bench for a timing simulation.