Timing constraints for output clock pin

[Altera_Forum]

I'm constraining a synchronous interface to a USB chip, and I've got all the timing constraints in for the data and control lines. Timequest is still listing the output clock itself as unconstrained. Do I need to constrain this? Ultimately as long as all the other constraints are met, I don't really care how much delay is present between the PLL clock output and the clock output pin. Should I set a false path to the output clock pin, or is there some other recommended thing to do? 

 Regards, David

[Altera_Forum]

as you have realised clk output does not need constraints by itself. to keep timequest happy set false path: 

 set_false_path -to [get_ports {clkout}]  exception to that if you need to treat it as any nonclk output

[Altera_Forum]

Thanks kaz!