Timing errors after rerunning the design

[Altera_Forum]

I have added timing constraints to my design and the time quest analyzer reported no timing errors  

 I made a very small changes in rtl file(added a register) and no change in the settings options when i runned again i see the tool reporting lot of timing errors  Why this happening when i have not changed the seed or any other option?  Do i need to logic-lock the region for using the same placement and routing which reported zero timing errors

[Altera_Forum]

There can be many cases. I cant comment as your info is very less. 

Were you closing timings with a small +ve slack before you added the register? Did you flopped a singlel bit signal or a bus?  Generally when we register a bus then we tend to increase the register count and then the routing congestion which can lead to setup failure at times (but depends).  If you were just closing timings before i.e. with a very small positive slack then it can fail timings as the place and route changes but i hope the WNS should not be much.

[Altera_Forum]

Run a seed sweep on the original, or the new one, and see what the variation is. (Tools -> Design Space Explorer -> Effort Level = Seed Sweep). All designs have a random variation that you need to work within. Look at the following for more info: 

http://www.alterawiki.com/wiki/the_quartus_ii_fitter_and_seed_sweeps If your design has variation where it sometimes makes timing and sometimes doesn't, you'll want to work on improving the overall timing. The first place to start is Tools -> Advisor -> Timing Optimization Advisor, which will show a lot of Quartus settings that can improve performance.

[Altera_Forum]

Thanks for all your advices