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Hi all,
I'm currently stuck with Video Over IP design on a Cyclone 3C40 board, reduced to ASI-to-Ethernet. The main problem concerns missing packets on the LAN (errors = missing CC frame under Wireshark & high number of corrupted packets under VLC). After deep observation of the first block "auk_ts_input.v" thanks to SignalTap II Logic Analyzer, output 32-bit frames (which feed UDP and RTP encapsulation blocks) seem to be already corrupted (transport stream CC field is not incrementing +1 for each PID packet but randomly +2 or +3). More exactly, the "ts_ready" signal is negated when a missing ts packet is engaged (byte 0x47). If we refer to Altera VoIP documentation : ---------------------------------------------------------------------------------------- ts_ready Output Flow control to TS source. The ts_ready signal is negated if the input buffer is full. If the TS source cannot be flow controlled, ensure that the input data rate is less than the RTP packet output rate. ---------------------------------------------------------------------------------------- My idea is now to include this "ts_ready" backpressure signal into a block which will preceed the "auk_ts_input.v" block, like this : (view atteched scheme) # does someone know an altera megawizard block which assumes this particular function ?? or maybe an opensource vhdl example ?? Thanks for your help guys and sorry for my poor language :-)Link Copied
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Sochuang: Download it yourself:
Altera website > Products > Literature > Application notes
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