Using LVDS in Stratix II

[Altera_Forum]

Hi everyone, 

 I've had a look through the other posts, but would just to clarify something about using LVDS with a Stratix II chip.  Using the ALTLVDS megawizard, I've created a LVDS receiver with 4 channels deserialized to 28. My confusion is that on the high speed side, there are only 4 rx_in lines, rather than 4 pairs, ie 8. Where do I get the differential pairs from? And how do I assign them to pins? I am using Quartus II v7.1.  Also, I've read that the Stratix II can configure termination resistors for these rx lines. How do I go about doing this?  Thanks in advance.  Adrian.

[Altera_Forum]

Open the AE: Assignments -> Assignment Editor 

In the To column, put in the name of your LVDS pins(you can use a wildcard) and choose the assignment name I/O Standard, then select the type LVDS. By assigning them to be differential, Quartus automatically assigns the (n) pin. So you only have to assign the location of the (p) pin. If you really want to, there is a way to add a differential buffer. I recommend against it since it is not necessary and makes your code less portable.  There is also a Termination assignment that allows you to choose the resitor type you want(assuming the architecture supports it). For a double-check, after your compiler open the report and go to Fitter -> Resource Section -> Input Pins/Output Pins, which give the I/O type and if a resistor is used for every pin.

[Altera_Forum]

Thanks for the help. 

 About the termination: What is meant by with or without calibration? And what is 'differential' termination (where it does not specify an ohm value)?