Using LVDS

[Altera_Forum]

Hello, 

 Could anybody please tell me how I can use the HSTC Connectors to communicate between two DE3 Boards?  I tried using bidirectional buffers to send/receive data over the pins, but that doesn't work.   Thank you! ~FPGAKitty~

[Altera_Forum]

--- Quote Start ---  I tried using bidirectional buffers to send/receive data over the pins, but that doesn't work.   --- Quote End ---   As explained in the DE3 User Manual, the male and female HSTC connectors have crossed LVDS Rx and Tx pins. You can either use fast differential LVDS connections, then you must follow the intended Tx and Rx assignment, or single ended connections with an arbitrary selected data direction. Also bidirectional I/Os are an option. But due to the said Tx/Rx crossing, you don't connect same pin numbers of adjacent boards.

[Altera_Forum]

Thanks Frank! To test out the connection, I simplified my design.  

 Example:  --- Quote Start ---   Board 1 and 2: input RECEIVING; output SENDING;   --- Quote End ---  I am assigning only the (p) pins in the qsf file, because I read that the (n) pins are automatically assigned by the fitter.    --- Quote Start ---   Board 1: set_location_assignment PIN_AC25 -to SENDING set_instance_assignment -name IO_STANDARD LVDS -to SENDING set_location_assignment PIN_AL32 -to RECEIVING set_instance_assignment -name IO_STANDARD LVDS -to RECEIVING Board 2: set_location_assignment PIN_AC25 -to SENDING set_instance_assignment -name IO_STANDARD LVDS -to SENDING set_location_assignment PIN_AL32 -to RECEIVING set_instance_assignment -name IO_STANDARD LVDS -to RECEIVING   --- Quote End ---  I am not using any megafunction, just using assign statements in Verilog. But I do not see the right result on SignalTap. "Receiving" which is an input to both boards (and an output from the other) is constantly high on both boards.   Can you please suggest what I may be doing wrong?

[Altera_Forum]

Did you check, if the correct VCCIO of 2.5 V is activated for the respectiv I/O bank, The DE3 board uses programmable VCCIOs that could be also switched off.

[Altera_Forum]

Thanks Frank! I apologize for my late reply. I did assign a VCCIO of 2.5 V to the I/O Groups using LVDS. I can cross check this with the LEDs by the power switch.  

 I am puzzled as to why this will not work. Do I need to assign clock signals to the CLKOUT/CLKIN Signals?  I get two warnings:   --- Quote Start ---  Pin "SENDING" is a differential I/O pin but does not have its complement pin. Hence, fitter automatically created the complement pin "SENDING(n)" Design has one or more differential I/O pins that do not connect to SERDES receiver or transmitter -- changes to this connectivity may affect fitting results  --- Quote End ---  ***  An unexpected event occured when I stacked the DE3s one atop the other. This causes all the HSTC's to connect, whether one intends to use them all or not. This results in not being able to use the DDR interfaces anymore, because the HSTC-B and the DDR interface share the same pins. However, one can mount the boards such that only one HSTC pair connects. Not quite the picture I had in mind.

[Altera_Forum]

The warnings are normal operation. 

 Generally, you can assign the LVDS I/O standard to I/O pins and the fitter will automatically assigning a differential pin pair. So I basically don't understand, why your interboard connection doesn't work.

[Altera_Forum]

I have attached the two files for the Top and Bottom FPGAs. The top one uses HSTC-C and the bottom one uses HSTC-A.  

 Please can you tell me if you see something incorrect?

[Altera_Forum]

No, I don't see a problem.

[Altera_Forum]

Thank you so much Frank!  

 I have no idea what I am doing incorrect. I am programming the FPGA's through two instances of Quartus running at the same time. Then I switch SW[0] to "On" on Board-0, the SENDING port on FPGA-0 shows the toggling I want to see. But on the Board-1 I never see any changes on RECEIVING port on FPGA.

[Altera_Forum]

To narrow down the problem, you should check the hardware signals at both involved boards. Can you observe correct LVDS signal levels at SENDING and RECEIVING pin pairs? Unfortunately I have no other suggestion.